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e 9/8/97 11:55 am 29060701.doc intel confidential (until publication date) preliminary information in this document is provided solely to enable use of intel products. intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of intel products except as provided in intel's terms and conditions of sale for such products. information contained herein supersedes previously published specifications on these devices from intel. ? intel corporation 1995 june 1997 order number: 290607-001 200-mhz pentium ? overdrive ? processor with mmx? technology to upgrade 100/133/166-mhz pentium processor-based systems 180-mhz pentium overdrive processor with mmx technology to upgrade 90/120/150-mhz pentium processor-based systems and upgrades 75-mhz pentium processor-based systems to 150-mhz 166-mhz pentium overdrive processor with mmx technology to upgrade 100/133- mhz pentium processor-based systems n n support for mmx? technology n n powerful processor upgrades for upgradable pentium ? processor-based systems n n superscalar architecture ? enhanced pipelines ? two pipelined integer units capable of 2 instructions/clock ? pipelined mmx unit ? pipelined floating-point unit n n separate code and data caches ? deeper write buffers, pool configuration ? enhanced branch prediction ? virtual mode extensions n n 32-bit cpu with 64-bit data bus n n .35 m m cmos silicon technology n n on-package voltage regulation and voltage filtering n n integrated fan/heatsink thermal solution n n compatible with installed software base ? ms-dos*, windows*, windows 95, windows nt, os/2*, unix* n n product line supports socket 5 & socket 7 designs n n 320 pin spga package n n bus/core ratio, hard-bonded in 2/5 and 1/3 modes n n easy installation n n supports 50, 60, 66-mhz bus speeds n n single 3.3 volt supply pentium? overdrive? processor with mmx ? technology for pentium processor-based systems
pentium ? overdrive ? processor with mmx ? technology e 2 9/8/97 11:55 am 29060701.doc intel confidential (until publication date) preliminary the pentium ? overdrive ? processor with mmx? technology is an end-user, single chip, pentium processor upgrade product. the end user is able to add support for intels new mmx technology and increase the performance of their pc by simply replacing the existing 75, 90, 100, 120, 133, 150, and 166-mhz pentium processor with a pentium overdrive processor with mmx technology. the pentium overdrive processor with mmx technology provides the performance needed for todays mainstream desktop applications and workstations. the pentium overdrive processor with mmx technology is binary compatible with the pentium processor and compatible with the entire installed base of applications for ms-dos*, windows*, windows 95, windows nt, os/2*, and unix*. the 200-mhz pentium overdrive processor with mmx technology is designed to upgrade 100, 133, and 166-mhz pentium processor-based systems. all most all of these systems use zif sockets that allow easy end user installation of the processor upgrade. the 180/150-mhz pentium overdrive processor with mmx technology is designed to upgrade 75, 90, 120, and 150-mhz pentium processor-based systems. the 166-mhz pentium overdrive processor with mmx technology is designed to upgrade 100 and 133-mhz pentium processor-based systems. the pentium overdrive processor with mmx technology for pentium processor-based systems has 4.5 million transistors and is built on intels advanced 0.35-micron silicon technology. the pentium overdrive processor with mmx technology is equipped with high reliability, integrated fan/heatsinks. technical product notice information in this document is provided in connection with intel products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the pentium overdrive processor with mmx technology may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product order. copies of documents which have an ordering number and are referenced in this document, or other intel literature, may be obtained from: intel corporation p.o. box 7641 mt. prospect il 60056-7641 or call 1-800-879-4683 or visit intels website at http://www.intel.com copyright ? intel corporation 1996, 1997. * third-party brands and names are the property of their respective owners.
e pentium ? overdrive ? processor with mmx ? technology 3 9/8/97 11:55 am 29060701.doc intel confidential (until publication date) preliminary contents page page 1.0. introduction ...............................................5 1.1. product overview...........................................5 1.2. product description ........................................8 1.3. purpose of this document ..............................8 1.4. compatibility note ..........................................8 2.0. pinout and pin description....................8 2.1. pinout..............................................................8 2.2. pin cross reference ....................................11 2.3. quick pin reference ....................................14 2.4. pin descriptions ...........................................22 2.4.1. input pins ..........................................22 2.4.2. output pins ......................................24 2.4.3. input/output pins ..........................25 2.4.4. pin grouping according to function ...........................................26 3.0. component operation...........................27 3.1. core to bus ratio for higher speed.............27 3.2. hardware interface differences ...................27 3.2.1. cputyp signal .................................27 3.3. processor initialization .................................27 3.3.1. power up specification..............27 3.3.2. test and configuration features (bist, frc, tristate test mode)........................................28 3.3.3. initialization with reset, init and bist .............................................28 3.4. instruction differences..................................28 3.4.1. mmx? technology extensions to the intel architecture........28 3.4.2. rdpmc (read performance monitoring counter) ..................28 3.5. cpuid ..........................................................28 3.6. on-package fan/heatsink ...........................30 3.7. on-package voltage regulator....................30 3.8. cache support..............................................30 3.9. code prefetch queue and branch target buffers ..........................................................30 3.10. i/o buffers ..................................................30 3.11. test register access .................................30 4.0. bios and software..................................31 5.0. electrical specifications...................31 5.1. power and ground .......................................31 5.2. decoupling recommendations.....................31 5.3. other connection recommendations ..........31 5.4. absolute maximum ratings..........................31 5.5. d.c. specifications .......................................33 5.6. a.c. specifications .......................................34 5.6.1. a. c. tables for a 50-mhz bus.....34 5.6.2. a. c. tables for a 60-mhz bus.....38 5.6.3. a. c. tables for a 66-mhz bus.....42 5.6.4. timing and waveforms ................46 6.0. mechanical specifications .................50 6.1. package dimensions....................................50 6.2. spatial requirements ...................................52 6.3. socket...........................................................53 6.3.1. socket compatibility ...................53 6.3.2. socket 5 pinout..............................53 6.3.3. socket 7 pinout..............................54 7.0. thermal specifications ........................57 8.0. testability ..................................................57 8.1. introduction ...................................................57 8.2. built in self test (bist) ................................57 8.3. tri-state test mode......................................57
pentium ? overdrive ? processor with mmx ? technology e 4 9/8/97 11:55 am 29060701.doc intel confidential (until publication date) preliminary figures figure 1. pentium ? overdrive ? processor with mmx? technology block diagram......6 figure 2. pentium ? overdrive ? processor with mmx? technology key features........7 figure 3. pentium ? overdrive ? processor with mmx? technology upgrade choices .7 figure 4. pentium ? overdrive ? processor with mmx? technology pinouttop side view ......................................................9 figure 5. pentium ? overdrive ? processor with mmx? technology pinoutpin side view ....................................................10 figure 6. pentium ? overdrive ? processor with mmx? technology with fan/heatsink30 figure 7. clock waveform..................................46 figure 8. valid delay timing ..............................46 figure 9. float delay timing ..............................47 figure 10. setup and hold timing......................47 figure 11. reset and configuration timing........48 figure 12. test timing........................................49 figure 13. reset and configuration timing........50 figure 14. pentium? overdrive? processor with mmx? technology package dimensions .........................................52 figure 15. illustrates physical space requirements for the pentium ? overdrive ? processor with mmx? technology..........................................53 figure 16. required free space from sides of spga package...................................53 figure 17. 320-pin socket 5...............................54 figure 18. pentium ? overdrive ? processor with mmx? technology pinouttop side view ....................................................55 figure 19. pentium ? overdrive ? processor with mmx? technology pinoutpin side view.....................................................56 tables table 1. 320-pin spga pin cross reference by pin name.........................................11 table 2. quick pin reference .............................14 table 3. input pins...............................................22 table 4. output pins............................................24 table 5. input/output pins...................................25 table 6. interprocessor i/o pins..........................25 table 7. pin functional grouping ........................26 table 8. pin functional groupings not supported by pentium ? overdrive ? processor with mmx? technology ......................27 table 9. core/bus frequencies...........................27 table 10. eax bit values definition for cpuid...29 table 11. eax bit values definition for processor type .....................................................29 table 12. absolute maximum ratings without fan/heatsink ........................................32 table 13. absolute maximum ratings for fan/heatsink only................................32 table 14. 3.3v d.c. specifications......................33 table 15. 50-mhz bus a.c. specifications .........34 table 16. 60-mhz bus a.c. specifications .........38 table 17. 66-mhz bus a.c. specifications .........42 table 18. pentium ? overdrive ? processor with mmx? technology package summary ..............................................50 table 19. package dimensions...........................51 table 20. design considerations ........................59
e pentium ? overdrive ? processor with mmx ? technology 5 9/8/97 11:55 am 29060701.doc intel confidential (until publication date) preliminary 1.0. introduction this datasheet describes intels pentium overdrive processor with mmx technology for upgradable pentium processor-based systems. the pentium overdrive processor with mmx technology currently includes upgrades for 75, 90, 100, 120, 133, 150, and 166-mhz pentium processors. technical descriptions of other pentium overdrive processors are available in intel overdrive ? processors datasheet (order #290436). this datasheet is intended to be used in conjunction with the pentium ? family users manual (order #241428), which describes the pentium family architecture and functionality. all enhancements or differences between the pentium overdrive processor with mmx technology and the original pentium processor (i.e., 75/90/100/120/133/150/ 166-mhz pentium processor vs. 200/180/166-mhz pentium overdrive processor with mmx technology) are described in this datasheet. pentium processor-based systems that are compatible with the pentium overdrive processor with mmx technology must be designed to both the original processor specifications and the pentium overdrive processor with mmx technology specifications. 1.1. product overview the pentium overdrive processor with mmx technology, for upgradable 75, 90, 100, 120, 150, and 166-mhz pentium systems, allows users to upgrade to more advanced pentium processor technology and adds intels new mmx technology. figure 1 contains the block diagram of the pentium overdrive processor with mmx technology. figure 2 lists some of the enhancements of the pentium overdrive processor with mmx technology. figure 3 describes the upgrade choices available for an existing pentium processor system.
pentium ? overdrive ? processor with mmx ? technology e 6 9/8/97 11:55 am 29060701.doc intel confidential (until publication date) preliminary 290607-1 figure 1. pentium ? overdrive ? processor with mmx? technology block diagram
e pentium ? overdrive ? processor with mmx ? technology 7 9/8/97 11:55 am 29060701.doc intel confidential (until publication date) preliminary l based on advanced pentium ? l .35 m m cmos silicon technology processor with mmx ? technology l dynamic branch prediction l superscalar architecture l improved execution time l pipelined floating-point unit l writeback mesi protocol in the data cache l separate 16k code and 16k data caches l bus cycle pipelining l 64 bit data bus l internal parity checking l address parity l performance monitoring l virtual mode extensions l execution tracing l system management mode l active fan/heatsink l fractional bus operation l for 75, 90, and 100-mhz pentium 200, 180, and 166-mhz pentium processor-based systems overdrive ? processors with mmx technology l 320 pin spga pinout l on-package voltage regulation 290607-2 figure 2. pentium ? overdrive ? processor with mmx? technology key features current pentium ? overdrive ? processor processor with mmx ? technology upgrade 75-mhz pentium processor 150-mhz pentium overdrive processor with mmx technology 90/120/150-mhz 180-mhz pentium overdrive pentium processor processor with mmx technology 100/133/166-mhz 200 & 166-mhz pentium overdrive pentium processor processor with mmx technology 290607-3 figure 3. pentium ? overdrive ? processor with mmx? technology upgrade choices
pentium ? overdrive ? processor with mmx ? technology e 8 9/8/97 11:55 am 29060701.doc intel confidential (until publication date) preliminary 1.2. product description the pentium overdrive processor with mmx technology comes in a 320-pin spga package and is a drop-in replacement for the 75, 90, 100, 120, 133, 150 and 166-mhz pentium processor. it comes with on-package voltage regulation to provide the required 2.8 volts for the core and a fan/heatsink for a complete thermal solution. the internal core operates at 3.0 and 2.5 times the speed of the system bus for respective 200mhz and 166-mhz pentium overdrive processor with mmx technology. for dual socket systems the original processor must be removed and the pentium overdrive processor with mmx technology should be installed in the secondary socket since it does not support dual processing. 1.3. purpose of this document this document describes the system architecture and physical environment of pentium overdrive processor with mmx technology. it also outlines differences between the originally installed pentium processor and the pentium overdrive processor with mmx technology. 1.4. compatibility note in this document some register bits are shown as intel reserved (res) and some pins are marked as no connects (nc) or reserved (res). when reserved bits are called out, treat them as fully undefined. this is essential for software compatibility with current and future processors. when a pin is marked as a nc or res it is important to not connect any other signals to such pins to ensure proper operation. intel strongly recommends following the guidelines below: 1. do not depend on the states of any unde fined bits when testing the values of defined register. mask them out when testing. 2. do not depend on the states of any unde fined bits when storing them to memory or another register. 3. do not depend on the ability to retain information written into any undefined bits. 4. when loading registers always load the undefined bits as zeros. 5. never connect signals to device pins marked nc or res. 6. inc pins are internal no-connects. this means that the pin is not connected to the processor internally. for example; the cputyp signal pin on the pentium overdrive processor with mmx technology is internally not connected to the package pin. the core is internally tied to v ss . the pin on the package is defined as inc. any external connections to the package pin will not affect the processor core because the core is physically disconnected from the package pin. 2.0. pinout and pin description 2.1. pinout the pentium overdrive processor with mmx technology has a 320-pin spga pinout and is designed to be installed into socket 5 or socket 7. see section 6.3 for more details on socket 5 and socket 7. figure 4 and figure 5 are illustrations of each side of the spga package.
e pentium ? overdrive ? processor with mmx ? technology 9 9/8/97 11:55 am 29060701.doc intel confidential (until publication date) preliminary 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 21 2 2 2 3 24 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 z y x w v u t s r q p n m l k j h g f e d c b a nc vcc5 vcc2 v ss v cc2 vss an am a l a k a j ah ag a f a e ad ac a b a a z y x w v u t s r q p n m l k j h g f e d c b a vcc5 a n a m a l a k a j a h a g a f a e a d a c a b a a 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 21 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 31 3 2 3 3 3 4 3 5 3 6 3 7 v ss vss vss vcc3 nc vcc3 vss vss n c v ss v cc2 v ss v ss v ss v cc3 n c v cc3 v ss vss v ss v ss vss vss vss vss vss vss vss vss vss vss vss d20 d16 d13 d 1 1 vss vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 d41 inc dp4 d45 d47 d38 d42 d36 d34 d32 d27 d29 d31 d25 dp2 d24 d50 d40 d44 d48 d39 d37 d35 d33 d28 d30 dp3 d26 d23 d19 d54 d46 d49 d52 dp6 dp5 d51 vcc2 d53 d55 vcc2 d58 d57 vcc2 d60 d61 vss d43 d56 dp7 d63 d59 d62 d21 d17 d14 d10 dp1 d12 d8 dp0 vcc3 vss d22 d18 d15 nc d9 d6 d7 d4 d5 d 1 d3 d2 picd0 picd1 vcc3 td i tdo cputyp trst# nc nc vss vcc3 nc nc frcmc# inc vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 breq inc vss vss vss vss vss vss vss vss vss vss ap adsc# ferr# pm0bp0 bp3 bp2 inv cache# mi/o# pm1bp1 ierr# ken# ewbe# na# brdyc# wb/wt# phit# boff# brdy# ahold apch k# pbreq# pcd smiact# hit# lock# pchk# pbgnt# ads# hlda hitm# pwt inc eads# d/c# ignne# init rs# nm i d/p# a2 3 intr smi# pen# a2 4 a2 7 a2 5 a3 1 a3 a7 a2 9 a2 6 a2 1 prdy phitm# hold flush# vcc2 vss w/r# vcc2 vss vcc2 vss vcc2 vss vcc2 vss vcc2 vss vcc3 vss vcc3 vss vcc3 vss vcc3 vss vcc3 vss a1 0 vss a8 a4 a3 0 a6 nc a2 8 a2 2 picclk d0 tck tms# nc vcc3 stpclk# inc buschk# a2 0m# be0# be1# be2# be3# be4# be5# be6# be7# scyc clk nc reset a2 0 a1 9 a1 8 a1 7 a1 6 a1 5 a1 4 a1 3 a1 2 a9 a1 1 a5 290607-4 figure 4. pentium ? overdrive ? processor with mmx? technology pinouttop side view
pentium ? overdrive ? processor with mmx ? technology e 10 9/8/97 11:55 am 29060701.doc intel confidential (until publication date) preliminary 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 z y x w v u t s r q p n m l k j h g f e d c b a nc vcc5 vcc2 v ss v c c2 vss a n a m a l a k a j a h a g a f a e a d a c a b a a z y x w v u t s r q p n m l k j h g f e d c b a vcc5 a n a m a l a k a j a h a g a f a e a d a c a b a a 1 0 11 12 13 1 4 1 5 16 17 1 8 1 9 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 v ss vss vss vcc3 nc vcc3 vss vss n c v ss v c c2 v ss v ss v ss v c c3 n c v c c3 v ss vss v ss v ss vss vss vss vss vss vss vss vss vss vss vss d20 d16 d13 d 1 1 vss vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 d41 inc dp4 d45 d47 d38 d42 d36 d34 d32 d27 d29 d31 d25 dp2 d24 d50 d40 d44 d48 d39 d37 d35 d33 d28 d30 dp3 d26 d23 d19 d54 d46 d49 d52 dp6 dp5 d 5 1 vcc2 d53 d55 vcc2 d58 d57 vcc2 d60 d61 vss d43 d56 dp 7 d63 d59 d62 d21 d1 7 d14 d10 dp1 d12 d8 dp0 vcc3 vss d22 d18 d1 5 nc d9 d6 d7 d4 d5 d 1 d3 d2 picd0 picd1 vcc3 td i tdo cputyp trst# nc nc vss vcc3 nc nc frcmc# inc vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 br eq inc vss vss vss vss vss vss vss vss vss vss ap adsc# ferr# pm0bp0 bp3 bp2 inv cache# mi/o# pm1bp1 ierr# ken# ewbe# na# brdyc# wb/wt# phit# boff# brdy# ahold apchk# pbreq# pcd smiact# hit# lock# pchk# pbgnt# ads# hlda hitm# pwt inc eads# d/c# ignne# init rs# nm i d/p# a23 intr smi# pen# a24 a27 a25 a31 a3 a7 a29 a26 a21 prdy phitm# hold flush# vcc2 vss w/r# vcc2 vss vcc2 vss vcc2 vss vcc2 vss vcc2 vss vcc3 vss vcc3 vss vcc3 vss vcc3 vss vcc3 vss a10 vss a8 a4 a30 a6 nc a28 a22 picclk d0 tck tms# nc vcc3 stpclk# inc buschk# a20m# be0# be1# be2# be3# be4# be5# be6# be7# scyc clk nc reset a20 a19 a18 a1 7 a16 a1 5 a14 a13 a12 a9 a 1 1 a5 290607-5 figure 5. pentium ? overdrive ? processor with mmx? technology pinoutpin side view
e pentium ? overdrive ? processor with mmx ? technology 11 9/8/97 11:55 am 29060701.doc intel confidential (until publication date) preliminary 2.2. pin cross reference table 1. 320-pin spga pin cross reference by pin name address signal location signal location signal location signal location signal location a3 al35 a9 ak30 a15 ak26 a21 af34 a27 ag33 a4 am34 a10 an31 a16 al25 a22 ah36 a28 ak36 a5 ak32 a11 al31 a17 ak24 a23 ae33 a29 ak34 a6 an33 a12 al29 a18 al23 a24 ag35 a30 am36 a7 al33 a13 ak28 a19 ak22 a25 aj35 a31 aj33 a8 am32 a14 al27 a20 al21 a26 ah34 data signal location signal location signal location signal location signal location d0 k34 d13 b34 d26 d24 d39 d10 d52 e03 d1 g35 d14 c33 d27 c21 d40 d08 d53 g05 d2 j35 d15 a35 d28 d22 d41 a05 d54 e01 d3 g33 d16 b32 d29 c19 d42 e09 d55 g03 d4 f36 d17 c31 d30 d20 d43 b04 d56 h04 d5 f34 d18 a33 d31 c17 d44 d06 d57 j03 d6 e35 d19 d28 d32 c15 d45 c05 d58 j05 d7 e33 d20 b30 d33 d16 d46 e07 d59 k04 d8 d34 d21 c29 d34 c13 d47 c03 d60 l05 d9 c37 d22 a31 d35 d14 d48 d04 d61 l03 d10 c35 d23 d26 d36 c11 d49 e05 d62 m04 d11 b36 d24 c27 d37 d12 d50 d02 d63 n03 d12 d32 d25 c23 d38 c09 d51 f04
pentium ? overdrive ? processor with mmx ? technology e 12 9/8/97 11:55 am 29060701.doc intel confidential (until publication date) preliminary table 1. 320-pin spga pin cross reference by pin name (continued) control signal location signal location signal location signal location a20m# ak08 brdyc# y03 flush# an07 pen# z34 ads# aj05 breq aj01 frcmc# y35 pm0/bp0 q03 adsc# am02 buschk# al07 hit# ak06 pm1/bp1 r04 ahold v04 cache# u03 hitm# al05 prdy ac05 ap ak02 cputyp** q35 hlda aj03 pwt al03 apchk# ae05 d/c# ak04 hold ab04 r/s# ac35 be0# al09 d/p#* ae35 ierr# p04 reset ak20 be1# ak10 dp0 d36 ignne# aa35 scyc al17 be2# al11 dp1 d30 init aa33 smi# ab34 be3# ak12 dp2 c25 intr/lint0 ad34 smiact# ag03 be4# al13 dp3 d18 inv u05 tck m34 be5# ak14 dp4 c07 ken# w05 tdi n35 be6# al15 dp5 f06 lock# ah04 tdo n33 be7# ak16 dp6 f02 m/io# t04 tms p34 boff# z04 dp7 n05 na# y05 trst# q33 bp2 s03 eads# am04 nmi/lint1 ac33 w/r# am06 bp3 s05 ewbe# w03 pcd ag05 wb/wt# aa05 brdy# x04 ferr# q05 pchk# af04 apic clock control dual processor private interface signal location signal location signal location picclk h34 clk ak18 pbgnt# ad04 picd0 j33 bf ** y33 pbreq# ae03 [dpen#] bf1** x34 phit# aa03 picd1 [apicen] l35 stpclk# v34 phitm# ac03 notes: the shaded pin definitions on the pentium ? overdrive ? processor with mmx? technology are dual processing pins and are not supported by the pentium overdrive processor with mmx technology in table 2. ? the d/p# signal in the 75, 90, 100, 120, 133, 150, and 166-mhz pentium processor is always driven. low indicates primary processor has the bus and high indicates the secondary processor is driving the bus. in the pentium overdrive processor with mmx technology this pin is defined internal no connect. ** these signals are internally set and are not connected to the pentium overdrive processor with mmx technology pins. the pins are defined as internal no-connects.
e pentium ? overdrive ? processor with mmx ? technology 13 9/8/97 11:55 am 29060701.doc intel confidential (until publication date) preliminary table 1. 320-pin spga pin cross reference by pin name (continued) v cc a07 a19 b02 g37 n01 t34 y01 ae01 aj29 an19 a09 a21 e15 j01 n37 u01 y37 ae37 an09 an21 a11 a23 e21 j37 q01 u33 aa01 ag01 an11 an23 a13 a25 e27 l01 q37 u37 aa37 ag37 an13 an25 a15 a27 e37 l33 s01 w01 ac01 aj11 an15 an27 a17 a29 g01 l37 s37 w37 ac37 aj19 an17 an29 v ss a03 b20 e23 m36 v02 ad02 aj17 am10 am26 b06 b22 e29 p02 v36 ad36 aj21 am12 am28 b08 b24 e31 p36 x02 af02 aj25 am14 am30 b10 b26 h02 r02 x36 af36 aj27 am16 an37 b12 b28 h36 r36 z02 ah02 aj31 am18 al01 b14 e11 k02 t02 z36 aj07 aj37 am20 b16 e13 k36 t36 ab02 aj09 al37 am22 b18 e19 m02 u35 ab36 aj13 am08 am24 nc/inc v cc5 a37 e25 s33 w33 c01 aj23 an35 an01 e17 r34 s35 w35 aj15 al19 an05 an03 note: the shaded v cc /v ss /nc pins are new pin definitions (additions) on the pentium ? overdrive ? processor with mmx? technology with the exception of a03 and b02.
pentium ? overdrive ? processor with mmx ? technology e 14 9/8/97 11:55 am 29060701.doc intel confidential (until publication date) preliminary 2.3. quick pin reference table 2. quick pin reference symbol type name and function a20m# i when the address bit 20 mask pin is asserted, pentium ? overdrive ? processor with mmx? technology emulates the address wraparound at 1 mbyte which occurs on the 8086. when a20m# is asserted, the pentium overdrive processor with mmx technology masks physical address bit 20 (a20) before performing a lookup to the internal caches or driving a memory cycle on the bus. the effect of a20m# is undefined in protected mode. a20m# must be asserted only when the processor is in real mode. a31-a3 i/o as outputs, the address lines of the processor along with the byte enables define the physical area of memory or i/o accessed. the external system drives the inquire address to the processor on a31-a3. ads# o the address status indicates that a new valid bus cycle is currently being driven by the pentium overdrive processor with mmx technology. adsc# o adsc# is functionally identical to ads#. ahold i in response to the assertion of address hold, pentium overdrive processor with mmx technology will stop driving the address lines (a31-a3), and ap in the next clock. the rest of the bus will remain active so data can be returned or driven for previously issued bus cycles. ap i/o address parity is driven by the pentium overdrive processor with mmx technology with even parity information on all the pentium overdrive processor with mmx technology generated cycles in the same clock that the address is driven. even parity must be driven back to the pentium overdrive processor with mmx technology during inquire cycles on this pin in the same clock as eads# to ensure that correct parity check status is indicated by the pentium overdrive processor with mmx technology apchk# o the address parity check status pin is asserted two clocks after eads# is sampled active if the pentium overdrive processor with mmx technology has detected a parity error on the address bus during inquire cycles. apchk# will remain active for one clock each time a parity error is detected (including during dual processing private snooping). [apicen] picd1 i the apic is not supported by the pentium overdrive processor with mmx technology. be7#-be5# be4#-be0# o i/o the byte enable pins are used to determine which bytes must be written to external memory, or which bytes were requested by the cpu for the current cycle. the byte enables are driven in the same clock as the address lines (a31-3). [bf] [bf1] i bus frequency determines the bus-to-core frequency ratio on the pentium processor. these are internal no connects on the pentium overdrive processor with mmx technology which has a preset bus fraction of 5/2 for 166- mhz overdrive processor and 3/1 for 200-mhz overdrive processor core/bus ratio.
e pentium ? overdrive ? processor with mmx ? technology 15 9/8/97 11:55 am 29060701.doc intel confidential (until publication date) preliminary table 2. quick pin reference (continued) symbol type name and function boff# i the backoff input is used to abort all outstanding bus cycles that have not yet completed. in response to boff#, the pentium overdrive processor with mmx technology will float all pins normally floated during bus hold in the next clock. the processor remains in bus hold until boff# is negated, at which time pentium overdrive processor with mmx technology restarts the aborted bus cycle(s) in their entirety. bp[3:2] pm/bp[1:0] o the breakpoint pins (bp3-0) correspond to the debug registers, dr3-dr0. these pins externally indicate a breakpoint match when the debug registers are programmed to test for breakpoint matches. bp1 and bp0 are multiplexed with the performance monitoring pins (pm1 and pm0). the pb1 and pb0 bits in the debug mode control register determine if the pins are configured as breakpoint or performance monitoring pins. the pins come out of reset configured for performance monitoring. brdy# i the burst ready input indicates that the external system has presented valid data on the data pins in response to a read or that the external system has accepted the pentium overdrive processor with mmx technology data in response to a write request. this signal is sampled in the t2, t12 and t2p bus states. brdyc# i this signal has the same functionality as brdy#. breq o the bus request output indicates to the external system that pentium overdrive processor with mmx technology has internally generated a bus request. this signal is always driven whether or not the pentium overdrive processor with mmx technology is driving its bus. buschk# i the bus check input allows the system to signal an unsuccessful completion of a bus cycle. if this pin is sampled active, pentium overdrive processor with mmx technology will latch the address and control signals in the machine check registers. if, in addition, the mce bit in cr4 is set, the pentium overdrive processor with mmx technology will vector to the machine check exception. cache# o for pentium overdrive processor with mmx technology-initiated cycles the cache pin indicates internal cacheability of the cycle (if a read), and indicates a burst writeback cycle (if a write). if this pin is driven inactive during a read cycle, pentium overdrive processor with mmx technology will not cache the returned data, regardless of the state of the ken# pin. this pin is also used to determine the cycle length (number of transfers in the cycle). clk i the clock input provides the fundamental timing for pentium overdrive processor with mmx technology. the clock frequency is the operating frequency of the pentium overdrive processor with mmx technology external bus and requires ttl levels. all external timing parameters except tdi, tdo, tms, trst#, and picd0-1 are specified with respect to the rising edge of clk. cputyp i cputyp is internally tied to ground and is a internal no-connect (inc) to the package pin on the pentium overdrive processor with mmx technology.
pentium ? overdrive ? processor with mmx ? technology e 16 9/8/97 11:55 am 29060701.doc intel confidential (until publication date) preliminary table 2. quick pin reference (continued) symbol type name and function d/c# o the data/code output is one of the primary bus cycle definition pins. it is driven valid in the same clock as the ads# signal is asserted. d/c# distinguishes between data and code or special cycles. d/p# o the pentium overdrive processor with mmx technology does not support dual processing. d63-d0 i/o these are the 64 data lines for the processor. lines d7-d0 define the least significant byte of the data bus; lines d63-d56 define the most significant byte of the data bus. when the cpu is driving the data lines, they are driven during the t2, t12, or t2p clocks for that cycle. during reads, the cpu samples the data bus when brdy# is returned. dp7-dp0 i/o these are the data parity pins for the processor. there is one for each byte of the data bus. they are driven by pentium overdrive processor with mmx technology with even parity information on writes in the same clock as write data. even parity information must be driven back to the pentium overdrive processor with mmx technology on these pins in the same clock as the data to ensure that the correct parity check status is indicated by the pentium overdrive processor with mmx technology. dp7 applies to d63-d56, dp0 applies to d7-d0. [dpen#] picd0 i/o the pentium overdrive processor with mmx technology does not support dual processing. eads# i this signal indicates that a valid external address has been driven onto the pentium overdrive processor with mmx technology address pins to be used for an inquire cycle. ewbe# i the external write buffer empty input, when inactive (high), indicates that a write cycle is pending in the external system. when pentium overdrive processor with mmx technology generates a write, and ewbe# is sampled inactive, the pentium overdrive processor with mmx technology will hold off all subsequent writes to all e- or m-state lines in the data cache until all write cycles have completed, as indicated by ewbe# being active. ferr# o the floating-point error pin is driven active when an unmasked floating-point error occurs. ferr# is similar to the error# pin on the intel387? math coprocessor. ferr# is included for compatibility with systems using dos-type floating-point error reporting. flush# i when asserted, the cache flush input forces the pentium overdrive processor with mmx technology to writeback all modified lines in the data cache and invalidate its internal caches. a flush acknowledge special cycle will be generated by the pentium overdrive processor with mmx technology indicating completion of the writeback and invalidation. if flush# is sampled low when reset transitions from high to low, tristate test mode is entered. frcmc# i the pentium overdrive processor with mmx technology does not support functional redundancy checking.
e pentium ? overdrive ? processor with mmx ? technology 17 9/8/97 11:55 am 29060701.doc intel confidential (until publication date) preliminary table 2. quick pin reference (continued) symbol type name and function hit# o the hit indication is driven to reflect the outcome of an inquire cycle. if an inquire cycle hits a valid line in either pentium overdrive processor with mmx technology data or instruction cache, this pin is asserted two clocks after eads# is sampled asserted. if the inquire cycle misses the pentium overdrive processor with mmx technology cache, this pin is negated two clocks after eads#. this pin changes its value only as a result of an inquire cycle and retains its value between the cycles. hitm# o the hit to a modified line output is driven to reflect the outcome of an inquire cycle. it is asserted after inquire cycles which resulted in a hit to a modified line in the data cache. it is used to inhibit another bus master from accessing the data until the line is completely written back. hlda o the bus hold acknowledge pin goes active in response to a hold request driven to the processor on the hold pin. it indicates that pentium overdrive processor with mmx technology has floated most of the output pins and relinquished the bus to another local bus master. when leaving bus hold, hlda will be driven inactive and pentium overdrive processor with mmx technology will resume driving the bus. if the pentium overdrive processor with mmx technology has a bus cycle pending, it will be driven in the same clock that hlda is de-asserted. hold i in response to the bus hold request, pentium overdrive processor with mmx technology will float most of its output and input/output pins and assert hlda after completing all outstanding bus cycles. the pentium overdrive processor with mmx technology will maintain its bus in this state until hold is de- asserted. hold is not recognized during lock cycles. the pentium overdrive processor with mmx technology will recognize hold during reset. ierr# o the internal error pin is used to indicate internal parity errors. if a parity error occurs on a read from an internal array, the pentium overdrive processor with mmx technology will assert the ierr# pin for one clock and then shutdown. ignne# i this is the ignore numeric error input. this pin has no effect when the ne bit in cr0 is set to 1. when the cr0.ne bit is 0, and the ignne# pin is asserted, the pentium overdrive processor with mmx technology will ignore any pending unmasked numeric exception and continue executing floating-point instructions for the entire duration that this pin is asserted. when the cr0.ne bit is 0, ignne# is not asserted, a pending unmasked numeric exception exists (sw.es = 1), and the floating-point instruction is one of finit, fclex, fstenv, fsave, fstsw, fstcw, feni, fdisi, or fsetpm, the pentium overdrive processor with mmx technology will execute the instruction in spite of the pending exception. when the cr0.ne bit is 0, ignne# is not asserted, a pending unmasked numeric exception exists (sw.es = 1), and the floating-point instruction is one other than finit, fclex, fstenv, fsave, fstsw, fstcw, feni, fdisi, or fsetpm, the pentium overdrive processor with mmx technology will stop execution and wait for an external interrupt.
pentium ? overdrive ? processor with mmx ? technology e 18 9/8/97 11:55 am 29060701.doc intel confidential (until publication date) preliminary table 2. quick pin reference (continued) symbol type name and function init i the pentium overdrive processor with mmx technology initialization input pin forces the pentium overdrive processor with mmx technology to begin execution in a known state. the processor state after init is the same as the state after reset except that the internal caches, write buffers, and floating- point registers retain the values they had prior to init. init may not be used in lieu of reset after power up. if init is sampled high when reset transitions from high to low, the pentium overdrive processor with mmx technology will perform built-in self test prior to the start of program execution. intr/lint0 i an active maskable interrupt input indicates that an external interrupt has been generated. if the if bit in the eflags register is set, the pentium overdrive processor with mmx technology will generate two locked interrupt acknowledge bus cycles and vector to an interrupt handler after the current instruction execution is completed. intr must remain active until the first interrupt acknowledge cycle is generated to assure that the interrupt is recognized. inv i the invalidation input determines the final cache line state (s or i) in case of an inquire cycle hit. it is sampled together with the address for the inquire cycle in the clock eads# is sampled active. ken# i the cache enable pin is used to determine whether the current cycle is cacheable or not and is consequently used to determine cycle length. when the pentium overdrive processor with mmx technology generates a cycle that can be cached (cache# asserted) and ken# is active, the cycle will be transformed into a burst line fill cycle. lock# o the bus lock pin indicates that the current bus cycle is locked. pentium overdrive processor with mmx technology will not allow a bus hold when lock# is asserted (but ahold and boff# are allowed). lock# goes active in the first clock of the first locked bus cycle and goes inactive after the brdy# is returned for the last locked bus cycle. lock# is guaranteed to be deasserted for at least one clock between back to back locked cycles. m/io# o the memory/input-output is one of the primary bus cycle definition pins. it is driven valid in the same clock as the ads# signal is asserted. m/io# distinguishes between memory and i/o cycles. na# i an active next address input indicates that the external memory system is ready to accept a new bus cycle although all data transfers for the current cycle have not yet completed. the pentium overdrive processor with mmx technology will issue ads# for a pending cycle two clocks after na# is asserted. the pentium overdrive processor with mmx technology supports up to 2 outstanding bus cycles. nmi/lint1 i the non-maskable interrupt request signal indicates that an external non- maskable interrupt has been generated. pbgnt# i/o the pentium overdrive processor with mmx technology does not support dual processing.
e pentium ? overdrive ? processor with mmx ? technology 19 9/8/97 11:55 am 29060701.doc intel confidential (until publication date) preliminary table 2. quick pin reference symbol type name and function pcd o the page cache disable pin reflects the state of the pcd bit in cr3, the page directory entry, or the page table entry. the purpose of pcd is to provide an external cacheability indication on a page by page basis. pchk# o the parity check output indicates the result of a parity check on a data read. it is driven with parity status two clocks after brdy# is returned. pchk# remains low one clock for each clock in which a parity error was detected. parity is checked only for the bytes on which valid data is returned. pen# i the parity enable input (along with cr4.mce) determines whether a machine check exception will be taken as a result of a data parity error on a read cycle. if this pin is sampled active in the clock a data parity error is detected, the pentium overdrive processor with mmx technology will latch the address and control signals of the cycle with the parity error in the machine check registers. if, in addition, the machine check enable bit in cr4 is set to 1, the pentium overdrive processor with mmx technology will vector to the machine check exception before the beginning of the next instruction. phit# i/o the pentium overdrive processor with mmx technology does not support dual processing. phitm# i/o the pentium overdrive processor with mmx technology does not support dual processing. picclk i the pentium overdrive processor with mmx technology does not support dual processing. picd0-1 [dpen#] [apicen] i/o the pentium overdrive processor with mmx technology does not support dual processing. pbreq# i/o the pentium overdrive processor with mmx technology does not support dual processing. pm/bp[1:0] o these pins function as part of the performance monitoring feature. the breakpoint 1-0 pins are multiplexed with the performance monitoring 1-0 pins. the pb1 and pb0 bits in the debug mode control register determine if the pins are configured as breakpoint or performance monitoring pins. the pins come out of reset configured for performance monitoring. prdy o the probe ready output pin indicates that the processor has stopped normal execution in response to the r/s# pin going active, or probe mode being entered. pwt o the page write through pin reflects the state of the pwt bit in cr3, the page directory entry, or the page table entry. the pwt pin is used to provide an external writeback indication on a page by page basis. r/s# i the run / stop input is an asynchronous, edge sensitive interrupt used to stop the normal execution of the processor and place it into an idle state. a high to low transition on the r/s# pin will interrupt the processor and cause it to stop execution at the next instruction boundary.
pentium ? overdrive ? processor with mmx ? technology e 20 9/8/97 11:55 am 29060701.doc intel confidential (until publication date) preliminary table 2. quick pin reference symbol type name and function reset i reset forces the pentium overdrive processor with mmx technology to begin execution at a known state. all pentium overdrive processor internal caches will be invalidated upon the reset. modified lines in the data cache are not written back. flush#, and init are sampled when reset transitions from high to low to determine if tristate test mode mode will be entered, or if bist will be run. scyc o the split cycle output is asserted during misaligned locked transfers to indicate that more than two cycles will be locked together. this signal is defined for locked cycles only. it is undefined for cycles which are not locked. smi# i the system management interrupt causes a system management interrupt request to be latched internally. when the latched smi# is recognized on an instruction boundary, the processor enters system management mode. smiact# o an active system management interrupt active output indicates that the processor is operating in system management mode (smm). stpclk# i assertion of the stop clock input signifies a request to stop the internal clock of the pentium overdrive processor with mmx technology thereby causing the core to consume less power. when the cpu recognizes stpclk#, the processor will stop execution on the next instruction boundary, unless superseded by a higher priority interrupt, and generate a stop grant acknowledge cycle. when stpclk# is asserted, the pentium overdrive processor with mmx technology will still respond to external snoop requests. tck i the testability clock input provides the clocking function for pentium overdrive processor with mmx technology boundary scan in accordance with the ieee boundary scan interface (standard 1149.1). it is used to clock state information and data into and out of the pentium overdrive processor with mmx technology during boundary scan. tdi i the test data input is a serial input for the test logic. tap instructions and data are shifted into the pentium overdrive processor with mmx technology on the tdi pin on the rising edge of tck when the tap controller is in an appropriate state. tdo o the test data output is a serial output of the test logic. tap instructions and data are shifted out of pentium overdrive processor with mmx technology on the tdo pin on tcks falling edge when the tap controller is in an appropriate state. tms i the value of the test mode select input signal sampled at the rising edge of tck controls the sequence of tap controller state changes. trst# i when asserted, the test reset input allows the tap controller to be asynchronously initialized. v cc2 i these 28 power inputs are defined separately so they may be used in a split voltage plane motherboard design. these pins must be supplied with 3.3v for the pentium overdrive processor with mmx technology to function.
e pentium ? overdrive ? processor with mmx ? technology 21 9/8/97 11:55 am 29060701.doc intel confidential (until publication date) preliminary table 2. quick pin reference (continued) symbol type name and function v cc3 i these 32 power inputs must be connected to 3.3v in either single or split voltage systems. v cc5 i the pentium overdrive processor with mmx technology has two 5v power inputs. v ss i the pentium overdrive processor with mmx technology has 68 ground inputs. w/r# o write/read is one of the primary bus cycle definition pins. it is driven valid in the same clock as the ads# signal is asserted. w/r# distinguishes between write and read cycles. wb/wt# i the writeback/writethrough input allows a data cache line to be defined as writeback or writethrough on a line by line basis. as a result, it determines whether a cache line is initially in the s or e state in the data cache. note: highlighted items in table 2 are signals not supported on the pentium ? overdrive ? processor with mmx? technology.
pentium ? overdrive ? processor with mmx ? technology e 22 9/8/97 11:55 am 29060701.doc intel confidential (until publication date) preliminary 2.4. pin descriptions 2.4.1. input pins table 3. input pins name active level synchronous/ asynchronous internal resistor qualified a20m# low asynchronous ahold high synchronous bf n/a synchronous/reset pulldown bf1 n/a synchronous/reset pullup boff# low synchronous brdy# low synchronous bus state t2,t12,t2p brdyc# low synchronous pullup bus state t2,t12,t2p buschk# low synchronous pullup brdy# clk n/a cputyp n/a synchronous/reset pulldown eads# low synchronous ewbe# low synchronous brdy# flush# low asynchronous frcmc# n/a asynchronous pullup hold high synchronous ignne# low asynchronous init high asynchronous intr high asynchronous inv high synchronous eads# ken# low synchronous first brdy#/na# na# low synchronous bus state t2,td,t2p nmi high asynchronous picclk n/a asynchronous pullup pen# low synchronous brdy# r/s# n/a asynchronous pullup
e pentium ? overdrive ? processor with mmx ? technology 23 9/8/97 11:55 am 29060701.doc intel confidential (until publication date) preliminary table 3. input pins (continued) name active level synchronous/ asynchronous internal resistor qualified reset high asynchronous smi# low asynchronous pullup stpclk# low asynchronous pullup tck n/a pullup tdi n/a synchronous/tck pullup tck tms n/a synchronous/tck pullup tck trst# low asynchronous pullup wb/wt# n/a synchronous first brdy#/na# note: highlighted signals are original pentium ? processor 75/90/100/120/133/150/166 mhz signals and are not supported by the pentium overdrive ? processor with mmx? technology.
pentium ? overdrive ? processor with mmx ? technology e 24 9/8/97 11:55 am 29060701.doc intel confidential (until publication date) preliminary 2.4.2. output pins table 4. output pins name active level when floated ads# low bus hold, boff# adsc# low bus hold, boff# apchk# low be7#-be5# low bus hold, boff# breq high cache# low bus hold, boff# d/p# n/a ferr# low hit# low hitm# low hlda high ierr# low lock# low bus hold, boff# m/io# , d/c# , w/r# n/a bus hold, boff# pchk# low bp3-2, pm1/bp1, pm0/bp0 high prdy high pwt, pcd high bus hold, boff# scyc high bus hold, boff# smiact# low tdo n/a all states except shift-dr and shift-ir notes: all output pins are floated during tristate test mode (except tdo). signals are original pentium ? processor signals and are not used by the pentium overdrive ? processor with mmx? technology.
e pentium ? overdrive ? processor with mmx ? technology 25 9/8/97 11:55 am 29060701.doc intel confidential (until publication date) preliminary 2.4.3. input/output pins table 5. input/output pins name active level when floated qualified (when an input) internal resistor a31-a3 n/a address hold, bus hold, boff# eads# ap n/a address hold, bus hold, boff# eads# be4#-be0# low bus hold, boff# reset pulldown d63-d0 n/a bus hold, boff# brdy# dp7-dp0 n/a bus hold, boff# brdy# picd0[dpen#] pullup picd1[apicen] pulldown notes: all input/output pins are floated during tristate test. signals are original pentium ? processor signals and are not used by the pentium overdrive ? processor with mmx? technology. table 6. interprocessor i/o pins name active level internal resistor phit# n/a pullup phitm# n/a pullup pbgnt# n/a pullup pbreq# n/a pullup note: signals are original pentium ? processor signals and are not used by the pentium overdrive ? processor with mmx? technology.
pentium ? overdrive ? processor with mmx ? technology e 26 9/8/97 11:55 am 29060701.doc intel confidential (until publication date) preliminary 2.4.4. pin grouping according to function table 7 organizes the pins with respect to their function. table 7. pin functional grouping function pins clock clk initialization reset, init address bus a31-a3, be7# - be0# address mask a20m# data bus d63-d0 address parity ap, apchk# data parity dp7-dp0, pchk#, pen# internal parity error ierr# system error buschk# bus cycle definition m/io#, d/c#, w/r#, cache#, scyc, lock# bus control ads#, adsc#, brdy#, brdyc#, na# page cacheability pcd, pwt cache control ken#, wb/wt# cache snooping/consistency ahold, eads#, hit#, hitm#, inv cache flush flush# write ordering ewbe# bus arbitration boff#, breq, hold, hlda interrupts intr, nmi floating-point error reporting ferr#, ignne# system management mode smi#, smiact# tap port tck, tms, tdi, tdo, trst# breakpoint/performance monitoring pm0/bp0, pm1/bp1, bp3-2 clock control stpclk# probe mode r/s#, prdy
e pentium ? overdrive ? processor with mmx ? technology 27 9/8/97 11:55 am 29060701.doc intel confidential (until publication date) preliminary table 8. pin functional groupings not supported by pentium ? overdrive ? processor with mmx? technology function pins apic support picclk, picd0-1 dual processing private bus control pbgnt#, pbreq#, phit#, phitm# functional redundancy checking frcmc# miscellaneous dual processing cputyp, d/p# execution tracing bt3-bt0, iu, iv, ibt 3.0. component operation 3.1. core to bus ratio for higher speed the pentium overdrive processor with mmx technology incorporates an internal phase lock loop (pll) and clock multiplier to generate the higher internal speeds. this allows the internal processor core to operate synchronously and at higher frequencies than the external bus. on the 200/180-mhz pentium overdrive processor with mmx technology, the bus fraction configuration will be preset to 3/1 internally and 166-mhz to 5/2. see table 9 for details. table 9. core/bus frequencies internal speed bus speed replaces (core/bus) 150-mhz 50-mhz 75/50-mhz 180-mhz 60-mhz 90/60-mhz 120/60-mhz 150/60-mhz 166-mhz 66-mhz 100/66-mhz 133/66-mhz 200-mhz 66-mhz 100/66-mhz 133/66-mhz 166/66-mhz 3.2. hardware interface differences the pentium overdrive processor with mmx technology is pin-for-pin compatible with the respective original pentium processors, except for the additional pins defined by socket 5 and 7 for the pentium overdrive processor with mmx technology. some minor differences are discussed in this section and are referenced in tables in previous section. these differences represent features that are not required for an end-user cpu upgrade. 3.2.1. cputyp signal the pentium overdrive processor with mmx technology cputyp signal is internally tied to ground and the signal pin on the package is an internal no-connect (inc). the original pentium processor must be removed for the pentium overdrive processor with mmx technology to function properly. 3.3. processor initialization 3.3.1. power up specification the pentium overdrive processor with mmx technology will boot like the respective original pentium processors. if the pentium overdrive processor with mmx technology is installed in a second socket of dual socket system the primary cpu must be removed or the system will not boot properly.
pentium ? overdrive ? processor with mmx ? technology e 28 9/8/97 11:55 am 29060701.doc intel confidential (until publication date) preliminary 3.3.2. test and configuration features (bist, frc, tristate test mode) the pentium overdrive processor with mmx technology will execute the built in self test (bist) and tristate test mode same as the respective original pentium processor. functional redundancy checking is not supported. 3.3.3. initialization with reset, init and bist the pentium overdrive processor with mmx technology handling of reset, init, and the built in self test (bist) is the same as the original pentium processors. the register states after reset, init, and bist are same as the original pentium processors. for further information refer to section 8 in this datasheet. 3.4. instruction differences the pentium overdrive processor with mmx technology is 100% compatible with the pentium processor (75-200). two additions have been made. the 57 instructions that comprise the mmx technology instruction set and the rdpmc (read performance monitoring counter) instruction. these new instructions are an added feature and will not impact the use of the upgraded system in anyway unless specifically used. 3.4.1. mmx? technology extensions to the intel architecture intels mmx technology is an extension to the intel architecture which provides for additional performance for multimedia and communications applications. intel processors that include this technology are still 100% compatible with all scalar intel processors. this means that all existing software that runs on existing intel processors will continue to run (without modification) on an intel processor that incorporates mmx technology. intels mmx technology uses a simd (single instruction, multiple data) tecnique to speedup multimedia and communications software by processing multiple data elements in parallel. the mmx instruction set all 57 new opcodes and a new 64-bit quadword type. the new 64-bit data type holds packed integer values. these packed integer values can be 8 bytes, 4 words, or 2 double-words. the pentium overdrive processor with mmx technology includes the mmx instruction set as defined by the intel architecture mmx? technology programmers reference manual (order #243007) and the intel architecture mmx? technology developers manual (order #243006). software can determine that the system has been upgraded to a intel architecture processor that supports mmx technology via the cpuid instruction. 3.4.2. rdpmc (read performance monitoring counter) rdpmc will enable the user to only read the performance monitoring counters. 3.5. cpuid the cpuid instruction allows software to determine the type and features of the microprocessor. when executing the cpuid instruction the pentium overdrive processor with mmx technology behaves like the original pentium processors: if the value in eax is 0 then the 12-byte ascii string genuineintel (little endian) is returned in ebx, edx, and ecx. also, a 1 is returned in eax. if the value in eax is 1 then the processor version is returned in eax and the processor capabilities are returned in edx. the values of eax and edx for the pentium ? overdrive ? processor with mmx? technology are given below. if the value in eax is neither 0 nor 1, pentium overdrive processor with mmx technology writes 0 to all registers or is undefined. the stepping field has the same format as the original pentium processor and will be the same for the pentium overdrive processor with mmx technology. the pentium overdrive processor with mmx technology will have a unique cpuid from the original pentium processor and the pentium processor with mmx technology (154xh vs. 052xh and 054xh). the type field is defined in table 11.
e pentium ? overdrive ? processor with mmx ? technology 29 9/8/97 11:55 am 29060701.doc intel confidential (until publication date) preliminary table 10. eax bit values definition for cpuid cpu 31...14 13...12 11...8 7...4 3...0 field definition (reserved) type family model stepping pentium ? processor (75, 90, 100) (reserved) table 11 5h 2h varies pentium processor with mmx? technology (166, 200, 233-mhz) (reserved) table 11 5h 4h varies pentium overdrive ? processor with mmx technology (reserved) table 11 5h 4h varies table 11. eax bit values definition for processor type bit 13 bit 12 processor type 0 0 primary pentium ? processor 0 0 primary pentium processor with mmx ? technology 0 1 pentium overdrive ? processor with mmx technology 1 0 dual pentium processor * 1 1 reserved note: * the pentium ? overdrive ? processor with mmx? technology does not support dual processing mode.
pentium ? overdrive ? processor with mmx ? technology e 30 9/8/97 11:55 am 29060701.doc intel confidential (until publication date) preliminary fan heatsink ceramic pga or spga 290607-6 figure 6. pentium ? overdrive ? processor with mmx? technology with fan/heatsink 3.6. on-package fan/heatsink the on-package fan/heatsink included with the pentium overdrive processor with mmx technology requires different stress ratings than the original pentium processor. the fan is a detachable unit, and the storage temperature is stated separately in table 12. operation of the pentium overdrive processor with mmx technology is def ined at t a = 10 c to 45 c. the fan/heatsink is shown in figure 6. 3.7. on-package voltage regulator the pentium overdrive processor with mmx technology has an on-package voltage regulator to supply 2.8 volts to the processor core. this allows the pentium overdrive processor with mmx technology to function in a 3.3 volt only system. 3.8. cache support the pentium overdrive processor with mmx technology has an enhanced internal cache (2x16kb total, 4 way set-associative code and data caches, each with improved tlbs) and will support the l2 caches supported by the pentium processor (75- 200). the pentium overdrive processor with mmx technology supports the intel 82430 chipsets. chipsets with 5v signal levels, 82497/82492 cache controller, and the 82498/82493 cache controller are not supported by the pentium overdrive processor with mmx technology. 3.9. code prefetch queue and branch target buffers code should not be written to rely on the specific code prefetch queue or branch target buffer mechanism of a particular processor. with each new generation and family of processors, these mechanisms are subject to change. 3.10. i/o buffers the pentium overdrive processor with mmx technology buffer models comply with the specifications for the buffer model for the respective original pentium processor. the circuit topology is the same and the ranges of values in the pentium overdrive processor with mmx technology model are within the original pentium processor ranges. the buffer models used by the pentium overdrive processor with mmx technology accurately model flight time and signal quality. 3.11. test register access the pentium overdrive processor with mmx technology have test registers which allow testing of different areas of the processor. these test registers are called model specific registers (msr). these msrs are accessed using the rdmsr and wrmsr instructions.
e pentium ? overdrive ? processor with mmx ? technology 31 9/8/97 11:55 am 29060701.doc intel confidential (until publication date) preliminary 4.0. bios and software the pentium overdrive processor with mmx technology is a drop-in replacement for the respective original pentium processor. bios changes are not normally neces sary but might be required. please call intel technical support hotline if assistance is required. pentium overdrive processor with mmx technology is 100% backward software compatible with their respective original pentium processors. 5.0. electrical specifications this section describes the electrical differences between the pentium processor (75-200) and the pentium overdrive processor with mmx technology. the pentium overdrive processor with mmx technology requires 3.3 volts to power the processor. the voltage to the socket is 3.3 volt and is converted by an on-package voltage regulator to the proper voltage for the processors internal core voltage plane. the internal 3.3 volt i/o plane is powered from the socket to the processor. the pentium overdrive processor with mmx technology looks like a 3.3 volt device externally. 5.1. power and ground for clean on-chip power distribution, the pentium overdrive processor with mmx technology in an spga package has 60 v cc (power) and 68 v ss (ground) inputs. the 28 v cc2 pins are connected internally to a power plane that provides power to the on-package voltage regulator for the core supply. the 32 v cc3 pins are connected internally to a separate power plane that provides power to the i/o buffers. power and ground connections must be made to all external v cc and v ss pins of the pentium overdrive processor with mmx technology. on the circuit board all v cc pins must be connected to a 3.3v v cc plane. all v ss pins must be connected to a v ss plane. the pentium overdrive processor with mmx technology pinout contains two 5v v cc pins (v cc5 ) used to provide power to the fan/heatsink. these pins should be connected to +5 volts 5% regardless of the system design. 5.2. decoupling recommendations decoupling recommendation for the original pentium processor apply to the pentium overdrive processor with mmx technology upgradable systems and capacitors should be placed near the pentium overdrive processor with mmx technology. the pentium overdrive processor with mmx technology can cause transient power surges, particularly when driving large capacitive loads. the pentium overdrive processor with mmx technology are shipped with adequate decoupling capacitors on the package to limit transients in excess of pentium processors tolerance. it is recommended to follow the original pentium processor specification for decoupling recommendations. 5.3. other connection recommendations for reliable operation, always connect unused inputs to an appropriate signal level. unused active low inputs should be connected to v cc . unused active high inputs should be connected to ground. all nc pins must remain unconnected. 5.4. absolute maximum ratings the tables in this section provide environmental stress ratings for the pentium overdrive processor with mmx technology. functional operation at the absolute maximum and minimum is not implied or guaranteed. extended exposure to maximum ratings may affect device reliability. furthermore, precautions should be taken to avoid high static voltages and electric fields to prevent static electric discharge. stressing the de vice beyond the absolute maximum ratings may cause permanent damage. the tables contain stress ratings only. operation beyond the operating conditions is not recommended and extended exposure beyond the operating conditions may effect device reliability.
pentium ? overdrive ? processor with mmx ? technology e 32 9/8/97 11:55 am 29060701.doc intel confidential (until publication date) preliminary table 12. absolute maximum ratings without fan/heatsink symbol parameter min max unit notes storage temperature -40 +125 0 c case temperature under bias -40 +110 0 c v cc3 3.3 v supply voltage with respect to v ss -0.5 +4.6 v v cc5 5 v supply voltage with respect to v ss -0.5 6.5 v v in 3.3 v only buffer dc input voltage -0.5 v cc3 +0.5v not to exceed 4.6v max v (2) v insb 5.0v safe buffer dc input voltage -0.5 +6.5 v (1) (3) notes: 1. applies to the clk and picclk. 2. applies to all pentium ? overdrive ? processor with mmx? technology inputs except clk and picclk. 3. see overshoot/undershoot transient specification in the pentium ? family users manual, volume 1. table 13. absolute maximum ratings for fan/heatsink only parameter min max unit notes fan: storage temperature -40 70 c case temperature under bias -5 60 c v cc5 5v fan supply voltage with respect to v ss -0.5 6.5 v
e pentium ? overdrive ? processor with mmx ? technology 33 9/8/97 1:25 pm 29060701.doc intel confidential (until publication date) preliminary 5.5. d.c. specifications the pentium overdrive processor with mmx technology will have compatible d.c. specifications to the original pentium processor, except for i cc (power supply current) and i cc5 (fan/heatsink current). the pentium overdrive processor with mmx technology voltage specification are v cc3 = 3.135v to 3.6v and v cc5 = 5v 5%. table 14 lists the d.c. specifications which apply to the pentium overdrive processor with mmx technology. the pentium overdrive processor with mmx technology requires a 3.3v power supply and 3.3v input signals with the exception of clk and signals which are 5v tolerant. table 14. 3.3v d.c. specifications v cc = 3.135v to 3.6v (see notes 6, 7 ), t a = 10 to 45 c symbol parameter min max unit notes v il input low voltage -0.3 0.8 v ttl level (3) v ih input high voltage 2.0 v cc + 0.3 v ttl level (3) v ol output low voltage 0.4 v ttl level (1) (3) v oh output high voltage 2.4 v ttl level (2) (3) v il5 input low voltage -0.3 0.8 v ttl level (8) v ih5 input high voltage 2.0 5.55 v ttl level (8) i cc5 fan/heatsink current 200 ma i cc3 power supply current 4330 4330 4330 4330 5000 ma ma ma ma ma @50/125 mhz (4)(5) @60/150 mhz (4)(5) @60/180 mhz (4)(5) @66/166 mhz (4)(5) @66/200 mhz (4)(5) i cc5 fan/heatsink current 200 ma i ccsb standby 450 770 ma notes: 1. parameter measured at 4 ma. 2. parameter measured at 3 ma. 3. 3.3 volt ttl levels apply to all signals except clk and picclk. 4. for worst case conditions: v cc3 +5% and t case = 10 o c. 5. power supply transient response and decoupling capacitors must be sufficient to handle the current transients required when transitioning from standby to full power mode. 6. refer to chapter 23 in the pentium ? family users manual, volume 1, for a listing of the remaining d.c. specifications. 7. the worst case ambient temperature is t a = 45 o c. 8. applies to 5v safe inputs: clk and picclk.
pentium ? overdrive ? processor with mmx ? technology e 34 9/8/97 11:55 am 29060701.doc intel confidential (until publication date) preliminary 5.6. a.c. specifications 5.6.1. a. c. tables for a 50-mhz bus the ac specifications of the 180/150-pentium overdrive processor with mmx technology consist of setup times, hold times, and valid delays at 0pf. the a.c. specifications given in table 15 consist of output delays, input setup requirements and input hold requirements for a 50-mhz external bus. all a.c. specifications (with the exception of those for the tap signals) are relative to the rising edge of the clk input. all timings are referenced to 1.5 volts for both 0 and 1 logic levels unless otherwise specified. within the sampling window, a synchronous input must be stable for correct 150-mhz pentium overdrive processor with mmx technology running 125-mhz operation. table 15. 50-mhz bus a.c. specifications 3.135 < v cc < 3.6v, ta = 10 to 45 c, c l = 0 pf symbol parameter min max unit figure notes frequency 25.0 50.0 mhz max core freq = 125 mhz @ 2/5 t 1a clk period 20.0 40.0 ns 7 t 1b clk period stability 250 ps 7 adjacent clocks, (1), (25) t 2 clk high time 4.0 ns 7 @2v, (1) t 3 clk low time 4.0 ns 7 @0.8v, (1) t 4 clk fall time 0.15 1.5 ns 7 (2.0v-0.8v), (1) t 5 clk rise time 0.15 1.5 ns 7 (0.8v-2.0v), (1) t 6a ads#, adsc#, pwt, pcd, be0-7#, m/io#, d/c#, cache#, scyc, w/r# valid delay 1.0 7.0 ns 8 t 6b ap valid delay 1.0 8.5 ns 8 t 6c a3-a31, lock# valid delay 1.1 7.0 ns 8 t 7 ads#, adsc#, ap, a3-a31, pwt, pcd, be0-7#, m/io#, d/c#, w/r#, cache#, scyc, lock# float delay 10.0 ns 8 (1) t 8 pchk#, apchk#, ierr#, ferr# valid delay 1.0 8.3 ns 8 (4) t 9 breq, hlda, smiact# valid delay 1.0 8.0 ns 8 (4) t 10a hit# valid delay 1.0 8.0 ns 8 t 10b hitm# valid delay 1.1 6.0 ns 8 t 11a pm0-1, bp0-3 valid delay 1.0 10.0 ns 8
e pentium ? overdrive ? processor with mmx ? technology 35 9/8/97 11:55 am 29060701.doc intel confidential (until publication date) preliminary table 15. 50-mhz bus a.c. specifications (continued) 3.135 < v cc < 3.6v, t a = 10 to 45 c, c l = 0 pf symbol parameter min max unit figure notes t 11b prdy valid delay 1.0 8.0 ns 8 t 12 d0-d63, dp0-7 write data valid delay 1.3 8.5 ns 8 t 13 d0-d63, dp0-3 write data float delay 10.0 ns 9 (1) t 14 a5-a31 setup time 6.5 ns 10 t 15 a5-a31 hold time 1.0 ns 10 t 16a inv, ap setup time 5.0 ns 10 t 16b eads# setup time 6.0 ns 10 t 17 eads#, inv, ap hold time 1.0 ns 10 t 18a ken# setup time 5.0 ns 10 t 18b na#, wb/wt# setup time 4.5 ns 10 t 19 ken#, wb/wt#, na# hold time 1.0 ns 10 t 20 brdy#, brdyc# setup time 5.0 ns 10 t 21 brdy#, brdyc# hold time 1.0 ns 10 t 22 boff# setup time 5.5 ns 10 t 22a ahold setup time 6.0 ns 10 t 23 ahold, boff# hold time 1.0 ns 10 t 24 buschk#, ewbe#, hold, pen# setup time 5.0 ns 10 t 25a buschk#, ewbe#, pen# hold time 1.0 ns 10 t 25b hold hold time 1.5 ns 10 t 26 a20m#, intr, stpclk# setup time 5.0 ns 10 (11), (15) t 27 a20m#, intr, stpclk# hold time 1.0 ns 10 (12) t 28 init, flush#, nmi, smi#, ignne# setup time 5.0 ns 10 (11), (15), (16) t 29 init, flush#, nmi, smi#, ignne# hold time 1.0 ns 10 (12) t 30 init, flush#, nmi, smi#, ignne# pulse width, async 2.0 clks (14), (16) t 31 r/s# setup time 5.0 ns 11 (11), (15), (16) t 32 r/s# hold time 1.0 ns 10 (12)
pentium ? overdrive ? processor with mmx ? technology e 36 9/8/97 11:55 am 29060701.doc intel confidential (until publication date) preliminary table 15. 50-mhz bus a.c. specifications 3.135 < v cc < 3.6v, ta = 10 to 45 c, c l = 0 pf symbol parameter min max unit figure notes t 33 r/s# pulse width, async. 2.0 clks (14), (16) t 34 d0-d63, dp0-7 read data setup time 3.8 ns 10 t 35 d0-d63, dp0-7 read data hold time 2.0 ns 10 t 36 reset setup time 5.0 ns 11 (11), (15) t 37 reset hold time 1.0 ns 11 (12) t 38 reset pulse width, v cc & clk stable 15.0 clks 11 (16) t 39 reset active after v cc & clk stable 1.0 ms 11 power up t 40 reset configuration signals (init, flush#) setup time 5.0 ns 11 (11), (15), (16) t 41 reset configuration signals (init, flush#) hold time 1.0 ns 11 (12) t 42a reset configuration signals (init, flush#) setup time, async. 2.0 clks 11 to reset falling edge (15) t 42b reset configuration signals (init, flush#, brdyc#, buschk#) hold time, async. 2.0 clks 11 to reset falling edge (20) t 42c reset configuration signals (brdyc#, buschk#) setup time, async. 3.0 clks 11 to reset falling edge (20) t 42d reset configuration signals (brdyc#) hold time, reset driven synchronously. 1.0 ns to reset falling edge (1), (27) t 44 tck frequency 16.0 mhz t 45 tck period 62.5 ns 7 t 46 tck high time 25.0 ns 7 @2v, (1) t 47 tck low time 25.0 ns 7 @0.8v, (1) t 48 tck fall time 5.0 ns 7 (2.0v-0.8v), (1), (8), (9) t 49 tck rise time 5.0 ns 7 (0.8v-2.0v), (1), (8), (9) t 50 trst# pulse width 40.0 ns 13 (1), asynchronous t 51 tdi, tms setup time 5.0 ns 12 (7) t 52 tdi, tms hold time 13.0 ns 12 (7) t 53 tdo valid delay 3.0 20.0 ns 12 (8)
e pentium ? overdrive ? processor with mmx ? technology 37 9/8/97 11:55 am 29060701.doc intel confidential (until publication date) preliminary table 15. 50-mhz bus a.c. specifications 3.135 < v cc < 3.6v, ta = 10 to 45 c, c l = 0 pf symbol parameter min max unit figure notes t 54 tdo float delay 25.0 ns 12 (1), (8) t 55 all non-test outputs valid delay 3.0 20.0 ns 12 (3), (8), (10) t 56 all non-test outputs float delay 25.0 ns 12 (1), (3), (8), (10) t 57 all non-test inputs setup time 5.0 ns 12 (3), (7), (10) t 58 all non-test inputs hold time 13.0 ns 12 (3), (7), (10) notes: notes 2, 6, and 13 are general and apply to all standard ttl signals used with the pentium ? overdrive processor with mmx? technology. 1. not 100% tested. guaranteed by design/characterization. 2. ttl input test waveforms are assumed to be 0 to 3 volt transitions with 1volt/ns rise and fall times. 3. non-test outputs and inputs are the normal output or input signals (besides tck, trst#, tdi, tdo, and tms). these timings correspond to the response of these signals due to boundary scan operations. 4. apchk#, ferr#, hlda, ierr#, lock#, and pchk# are glitch free outputs. glitch free signals monotonically transition without false transitions (i.e., glitches). 5. 0.8 v/ns <= clk input rise/fall time <= 8 v/ns. 6. 0.3 v/ns <= input rise/fall time <= 5 v/ns. 7. referenced to tck rising edge. 8. referenced to tck falling edge. 9. 1ns can be added to the max tck rise and fall times for every 10 mhz of frequency below 33 mhz. 10. during probe mode operation, do not use the boundary scan timings (t 55-58 ). 11. setup time is required to guarantee recognition on a specific clock. this is not applicable to the pentium overdrive processor with mmx technology. 12. hold time is required to guarantee recognition on a specific clock. 13. all ttl timings are referenced from 1.5 v. 14. to guarantee proper asynchronous recognition, the signal must have been deasserted (inactive) for a minimum of 2 clocks before being returned active and must meet the minimum pulse width. 15. this input may be driven asynchronously. however, when operating the pentium ? overdrive ? processor with mmx? technology, flush# and reset must be asserted synchronously. 16. when driven asynchronously, reset, nmi, flush#, r/s#, init, and smi# must be deasserted (inactive) for a minimum of 2 clocks before being returned active. 17. the d/c#, m/io#, w/r#, cache#, and a5-a31 signals are sampled only on the clk that ads# is active. 18. bf, bf1, and cputyp should be strapped to v cc or v ss . 19. these signals are measured on the rising edge of adjacent clks at 1.5v. to ensure a 1:1 relationship between the amplitude of the input jitter and the internal and external clocks, the jitter frequency specturm should not have any power spectrum peaking between 500khz and 1/3 of the clk operating frequency. the amount of jitter present must be accounted for as a component of clk skew between devices. 20. brdyc# and buschk# are used as reset configuration signals to select buffer size. 21. the value of this signal may have been changed, check the latest pentium processor data book for the updated values. ** each valid delay is specified for a 0 pf load. the system designer should use i/o buffer modeling to account for signal flight time delays.
pentium ? overdrive ? processor with mmx ? technology e 38 9/8/97 11:55 am 29060701.doc intel confidential (until publication date) preliminary 5.6.2. a. c. tables for a 60-mhz bus the a.c. specifications given in table 16 consist of output delays, input setup requirements and input hold requirements for a 60-mhz external bus. all a.c. specifications (with the exception of those for the tap signals) are relative to the rising edge of the clk input. all timings are referenced to 1.5 volts for both 0 and 1 logic levels unless otherwise specified. within the sampling window, a synchronous input must be stable for correct 180-mhz pentium overdrive processor with mmx technology operation. table 16. 60-mhz bus a.c. specifications 3.135 < v cc < 3.6v, t a = 10 to 45 c, c l = 0 pf symbol parameter min max unit figure notes frequency 30 60.0 mhz max core freq = 150 mhz @ 2/5 t 1a clk period 16.67 33.33 ns 7 t 1b clk period stability 250 ps 7 adjacent clocks, (1), (25) t 2 clk high time 4.0 ns 7 @2v, (1) t 3 clk low time 4.0 ns 7 @0.8v, (1) t 4 clk fall time 0.15 1.5 ns 7 (2.0v-0.8v), (1) t 5 clk rise time 0.15 1.5 ns 7 (0.8v-2.0v), (1) t 6a ads#, adsc#, pwt, pcd, be0-7#, m/io#, d/c#, w/r#, cache#, scyc valid delay 1.0 7.0 ns 8 t 6b ap valid delay 1.0 8.5 ns 8 t 6c a3-a31, lock# valid delay 1.1 7.0 ns 8 t 7 ads#, adsc#, ap, a3-a31, pwt, pcd, be0-7#, m/io#, d/c#, w/r#, cache#, scyc, lock# float delay 10.0 ns 9 (1) t 8a apchk#, ierr#, ferr# valid delay 1.0 8.3 ns 8 (4) t 8b pchk# valid delay 1.0 7.8 ns 8 (4) t 9a breq, hlda valid delay 1.0 8.0 ns 8 (4) t 9b smiact# valid delay 1.0 7.6 ns 8 (4) t 10a hit# valid delay 1.0 8.0 ns 8 t 10b hitm# valid delay 1.1 6.0 ns 8 t 11a pm0-1, bp0-3 valid delay 1.0 10.0 ns 8 t 11b prdy valid delay 1.0 8.0 ns 8 t 12 d0-d63, dp0-7 write data valid delay 1.3 7.5 ns 8
e pentium ? overdrive ? processor with mmx ? technology 39 9/8/97 11:55 am 29060701.doc intel confidential (until publication date) preliminary table 16. 60-mhz bus a.c. specifications (continued) 3.135 < v cc < 3.6v, t a = 10 to 45 c, c l = 0 pf symbol parameter min max unit figure notes t 13 d0-d63, dp0-3 write data float delay 10.0 ns 9 (1) t 14 a5-a31 setup time 6.0 ns 10 t 15 a5-a31 hold time 1.0 ns 8 t 16a inv, ap setup time 5.0 ns 8 t 16b eads# setup time 5.5 ns 8 t 17 eads#, inv, ap hold time 1.0 ns 8 t 18a ken# setup time 5.0 ns 8 t 18b na#, wb/wt# setup time 4.5 ns 8 t 19 ken#, wb/wt#, na# hold time 1.0 ns 8 t 20 brdy#, brdyc# setup time 5.0 ns 8 t 21 brdy#, brdyc# hold time 1.0 ns 8 t 22 ahold, boff# setup time 5.5 ns 8 t 23 ahold, boff# hold time 1.0 ns 8 t 24 buschk#, ewbe#, hold, pen# setup time 5.0 ns 8 t 25 buschk#, ewbe#, pen# hold time 1.0 ns 8 t 25a hold hold time 1.5 ns 8 t 26 a20m#, intr, stpclk# setup time 5.0 ns 8 (11), (15) t 27 a20m#, intr, stpclk# hold time 1.0 ns 8 (12) t 28 init, flush#, nmi, smi#, ignne# setup time 5.0 ns 8 (11), (15), (16) t 29 init, flush#, nmi, smi#, ignne# hold time 1.0 ns 8 (12) t 30 init, flush#, nmi, smi#, ignne# pulse width, async 2.0 clks (14), (16) t 31 r/s# setup time 5.0 ns 8 (11), (15), (16) t 32 r/s# hold time 1.0 ns 8 (12) t 33 r/s# pulse width, async. 2.0 clks (14), (16) t 34 d0-d63, dp0-7 read data setup time 3.0 ns 8 t 35 d0-d63, dp0-7 read data hold time 1.5 ns 8
pentium ? overdrive ? processor with mmx ? technology e 40 9/8/97 11:55 am 29060701.doc intel confidential (until publication date) preliminary table 16. 60-mhz bus a.c. specifications (continued) 3.135 < v cc < 3.6v, t a = 10 to 45 c, c l = 0 pf symbol parameter min max unit figure notes t 36 reset setup time 5.0 ns 9 (11), (15) t 37 reset hold time 1.0 ns 9 (12) t 38 reset pulse width, v cc & clk stable 15 clks 9 (16) t 39 reset active after v cc & clk stable 1.0 ms 9 power up t 40 reset configuration signals (init, flush#) setup time 5.0 ns 9 (11), (15), (16) t 41 reset configuration signals (init, flush#) hold time 1.0 ns 9 (12) t 42a reset configuration signals (init, flush#) setup time, async. 2.0 clks 9 (15) t 42b reset configuration signals (flush#, brdyc#, init, buschk#) hold time, async. 2.0 clks 9 (20) t 42c reset configuration signals (brdyc#, buschk#) setup time, async. 3.0 clks 9 (20) t 42d reset configuration signals (brdyc#) hold time, reset driven synchronously. 1.0 ns to reset falling edge (1), (27) t 44 tck frequency 16.0 mhz t 45 tck period 62.5 ns 7 t 46 tck high time 25.0 ns 7 @2v, (1) t 47 tck low time 25.0 ns 7 @0.8v, (1) t 48 tck fall time 5.0 ns 7 (2.0v-0.8v), (1), (8), (9) t 49 tck rise time 5.0 ns 7 (0.8v-2.0v), (1), (8), (9) t 50 trst# pulse width 40.0 ns 13 asynchronous, (1) t 51 tdi, tms setup time 5.0 ns 12 (7) t 52 tdi, tms hold time 13.0 ns 12 (7) t 53 tdo valid delay 3.0 20.0 ns 12 (8) t 54 tdo float delay 25.0 ns 12 (1), (8) t 55 all non-test outputs valid delay 3.0 20.0 ns 12 (3), (8), (10) t 56 all non-test outputs float delay 25.0 ns 12 (1), (3), (8), (10)
e pentium ? overdrive ? processor with mmx ? technology 41 9/8/97 11:55 am 29060701.doc intel confidential (until publication date) preliminary table 16. 60-mhz bus a.c. specifications (continued) 3.135 < v cc < 3.6v, t a = 10 to 45 c, c l = 0 pf symbol parameter min max unit figure notes t 57 all non-test inputs setup time 5.0 ns 12 (3), (7), (10) t 58 all non-test inputs hold time 13.0 ns 12 (3), (7), (10) notes: notes 2, 6, and 13 are general and apply to all standard ttl signals used with the pentium ? overdrive processor with mmx? technology. 1. not 100% tested. guaranteed by design/characterization. 2. ttl input test waveforms are assumed to be 0 to 3 volt transitions with 1volt/ns rise and fall times. 3. non-test outputs and inputs are the normal output or input signals (besides tck, trst#, tdi, tdo, and tms). these timings correspond to the response of these signals due to boundary scan operations. 4. apchk#, ferr#, hlda, ierr#, lock#, and pchk# are glitch free outputs. glitch free signals monotonically transition without false transitions (i.e., glitches). 5. 0.8 v/ns <= clk input rise/fall time <= 8 v/ns. 6. 0.3 v/ns <= input rise/fall time <= 5 v/ns. 7. referenced to tck rising edge. 8. referenced to tck falling edge. 9. 1ns can be added to the max tck rise and fall times for every 10 mhz of frequency below 33 mhz. 10. during probe mode operation, do not use the boundary scan timings (t 55-58 ). 11. setup time is required to guarantee recognition on a specific clock. this is not applicable to the pentium overdrive processor with mmx technology. 12. hold time is required to guarantee recognition on a specific clock. 13. all ttl timings are referenced from 1.5 v. 14. to guarantee proper asynchronous recognition, the signal must have been deasserted (inactive) for a minimum of 2 clocks before being returned active and must meet the minimum pulse width. 15. this input may be driven asynchronously. however, when operating the pentium ? overdrive ? processor with mmx? technology, flush# and reset must be asserted synchronously. 16. when driven asynchronously, reset, nmi, flush#, r/s#, init, and smi# must be deasserted (inactive) for a minimum of 2 clocks before being returned active. 17. the d/c#, m/io#, w/r#, cache#, and a5-a31 signals are sampled only on the clk that ads# is active. 18. bf, bf1, and cputyp should be strapped to v cc or v ss . 19. these signals are measured on the rising edge of adjacent clks at 1.5v. to ensure a 1:1 relationship between the amplitude of the input jitter and the internal and external clocks, the jitter frequency specturm should not have any power spectrum peaking between 500khz and 1/3 of the clk operating frequency. the amount of jitter present must be accounted for as a component of clk skew between devices. 20. brdyc# and buschk# are used as reset configuration signals to select buffer size. 21. the value of this signal may have been changed, check the latest pentium processor data book for the updated values. ** each valid delay is specified for a 0 pf load. the system designer should use i/o buffer modeling to account for signal flight time delays.
pentium ? overdrive ? processor with mmx ? technology e 42 9/8/97 11:55 am 29060701.doc intel confidential (until publication date) preliminary 5.6.3. a. c. tables for a 66-mhz bus the a.c. specifications given in table 17 consist of output delays, input setup requirements and input hold requirements for a 66-mhz external bus. all a.c. specifications (with the exception of those for the tap signals) are relative to the rising edge of the clk input. all timings are referenced to 1.5 volts for both 0 and 1 logic levels unless otherwise specified. within the sampling window, a synchronous input must be stable for correct 200-mhz pentium overdrive processor with mmx technology operation. table 17. 66-mhz bus a.c. specifications 3.135 < v cc < 3.6v, t a = 10 to 45 c, c l = 0 pf symbol parameter min max unit figure notes frequency 33.33 66.6 mhz max core freq = 166 mhz @ 2/5 t 1a clk period 15.0 30.0 ns 7 t 1b clk period stability 250 ps 7 adjacent clocks, (1), (25) t 2 clk high time 4.0 ns 7 @2v, (1), (5) t 3 clk low time 4.0 ns 7 @0.8v, (1), (5) t 4 clk fall time 0.15 1.5 ns 7 (2.0v-0.8v),(1),(5) t 5 clk rise time 0.15 1.5 ns 7 (0.8v-.0v),(1),(5) t 6a adsc#, pwt, pcd, be0-7#, d/c#, w/r#, cache#, scyc, valid delay 1.0 7.0 ns 8 t 6b ap valid delay 1.0 8.5 ns 8 t 6c a3-a31, lock# valid delay 1.1 7.0 ns 8 t 6d ads#, mio# valid delay 1.0 6.0 ns 8 t 7 ads#, adsc#, ap, a3-a31, pwt, pcd, be0-7#, m/io#, d/c#, w/r#, cache#, scyc, lock# float delay 10.0 ns 9 (1) t 8a apchk#, ierr#, ferr# valid delay 1.0 8.3 ns 8 (4) t 8b pchk# valid delay 1.0 7.0 ns 8 (4) t 9a breq, hlda valid delay 1.0 8.0 ns 8 (4), (21) t 9b smiact# valid delay 1.0 7.6 ns 8 (4), (21) t 10a hit# valid delay 1.0 8.0 ns 8 (21) t 10b hitm# valid delay 1.1 6.0 ns 8 t 11a pm0-1, bp0-3 valid delay 1.0 10.0 ns 8 t 11b prdy valid delay 1.0 8.0 ns 8 t 12 d0-d63, dp0-7 write data valid delay 1.3 7.5 ns 8 (21)
e pentium ? overdrive ? processor with mmx ? technology 43 9/8/97 11:55 am 29060701.doc intel confidential (until publication date) preliminary table 17. 66-mhz bus a.c. specifications (continued) 3.135 < v cc < 3.6v, t a = 10 to 45 c, c l = 0 pf symbol parameter min max unit figure notes t 13 d0-d63, dp0-3 write data float delay 10.0 ns 9 (1) t 14 a5-a31 setup time 6.0 ns 10 t 15 a5-a31 hold time 1.0 ns 10 t 16a inv, ap setup time 5.0 ns 10 t 16b eads# setup time 5.5 ns 10 t 17 eads#, inv, ap hold time 1.0 ns 10 t 18a ken# setup time 5.0 ns 10 t 18b na#, wb/wt# setup time 4.5 ns 10 t 19 ken#, wb/wt#, na# hold time 1.0 ns 10 t 20 brdy#, brdyc# setup time 5.0 ns 10 t 21 brdy#, brdyc# hold time 1.0 ns 10 t 22 ahold, boff# setup time 5.5 ns 10 t 23 ahold, boff# hold time 1.0 ns 10 t 24 buschk#, ewbe#, hold, pen# setup time 5.0 ns 10 t 25a buschk#, ewbe#, pen# hold time 1.0 ns 10 t 25b hold hold time 1.5 ns 10 t 26 a20m#, intr, stpclk# setup time 5.0 ns 10 (11), (15) t 27 a20m#, intr, stpclk# hold time 1.0 ns 10 (12) t 28 init, flush#, nmi, smi#, ignne# setup time 5.0 ns 10 (11), (15), (16) t 29 init, flush#, nmi, smi#, ignne# hold time 1.0 ns 10 (12) t 30 init, flush#, nmi, smi#, ignne# pulse width, async 2.0 clks (14), (16) t 31 r/s# setup time 5.0 ns 10 (11), (15), (16) t 32 r/s# hold time 1.0 ns 10 (12) t 33 r/s# pulse width, async. 2.0 clks (14), (16) t 34 d0-d63, dp0-7 read data setup time 3.0 ns 10 (21) t 35 d0-d63, dp0-7 read data hold time 2.0 ns 10 (21)
pentium ? overdrive ? processor with mmx ? technology e 44 9/8/97 11:55 am 29060701.doc intel confidential (until publication date) preliminary table 17. 66-mhz bus a.c. specifications (continued) 3.135 < v cc < 3.6v, t a = 10 to 45 c, c l = 0 pf symbol parameter min max unit figure notes t 36 reset setup time 5.0 ns 11 (11), (15) t 37 reset hold time 1.0 ns 11 (12) t 38 reset pulse width, v cc & clk stable 15.0 clks 11 (16) t 39 reset active after v cc & clk stable 1.0 ms 11 power up t 40 reset configuration signals (init, flush#) setup time 5.0 ns 11 (11), (15), (16) t 41 reset configuration signals (init, flush#) hold time 1.0 ns 11 (12) t 42a reset configuration signals (init, flush#) setup time, async. 2.0 clks 11 to reset falling edge (15) t 42b reset configuration signals (init, flush#,brdyc#, buschk#) hold time, async. 2.0 clks 11 to reset falling edge (20) t 42c reset configuration signals (brdyc#, buschk#) setup time, async. 3.0 clks 11 to reset falling edge (20) t 42d reset configuration signals (brdyc#) hold time, reset driven synchronously. 1.0 ns to reset falling edge (1), (27) t 44 tck frequency 16.0 mhz t 45 tck period 62.5 ns 7 t 46 tck high time 25.0 ns 7 @2v, (1) t 47 tck low time 25.0 ns 7 @0.8v, (1) t 48 tck fall time 5.0 ns 7 (2.0v-0.8v), (1), (8), (9) t 49 tck rise time 5.0 ns 7 (0.8v-2.0v), (1), (8), (9) t 50 trst# pulse width 40.0 ns 13 asynchronous, (1) t 51 tdi, tms setup time 5.0 ns 12 (7) t 52 tdi, tms hold time 13.0 ns 12 (7) t 53 tdo valid delay 3.0 20.0 ns 12 (8) t 54 tdo float delay 25.0 ns 12 (1), (8) t 55 all non-test outputs valid delay 3.0 20.0 ns 12 (3), (8), (10)
e pentium ? overdrive ? processor with mmx ? technology 45 9/8/97 11:55 am 29060701.doc intel confidential (until publication date) preliminary table 17. 66-mhz bus a.c. specifications (continued) 3.135 < v cc < 3.6v, t a = 10 to 45 c, c l = 0 pf symbol parameter min max unit figure notes t 56 all non-test outputs float delay 25.0 ns 12 (1), (3), (8), (10) t 57 all non-test inputs setup time 5.0 ns 12 (3), (7), (10) t 58 all non-test inputs hold time 13.0 ns 12 (3), (7), (10) notes: notes 2, 6, and 13 are general and apply to all standard ttl signals used with the pentium ? overdrive processor with mmx? technology. 1. not 100% tested. guaranteed by design/characterization. 2. ttl input test waveforms are assumed to be 0 to 3 volt transitions with 1volt/ns rise and fall times. 3. non-test outputs and inputs are the normal output or input signals (besides tck, trst#, tdi, tdo, and tms). these timings correspond to the response of these signals due to boundary scan operations. 4. apchk#, ferr#, hlda, ierr#, lock#, and pchk# are glitch free outputs. glitch free signals monotonically transition without false transitions (i.e., glitches). 5. 0.8 v/ns <= clk input rise/fall time <= 8 v/ns. 6. 0.3 v/ns <= input rise/fall time <= 5 v/ns. 7. referenced to tck rising edge. 8. referenced to tck falling edge. 9. 1ns can be added to the max tck rise and fall times for every 10 mhz of frequency below 33 mhz. 10. during probe mode operation, do not use the boundary scan timings (t 55-58 ). 11. setup time is required to guarantee recognition on a specific clock. this is not applicable to the pentium overdrive processor with mmx technology. 12. hold time is required to guarantee recognition on a specific clock. 13. all ttl timings are referenced from 1.5 v. 14. to guarantee proper asynchronous recognition, the signal must have been deasserted (inactive) for a minimum of 2 clocks before being returned active and must meet the minimum pulse width. 15. this input may be driven asynchronously. however, when operating the pentium ? overdrive ? processor with mmx? technology, flush# and reset must be asserted synchronously. 16. when driven asynchronously, reset, nmi, flush#, r/s#, init, and smi# must be deasserted (inactive) for a minimum of 2 clocks before being returned active. 17. the d/c#, m/io#, w/r#, cache#, and a5-a31 signals are sampled only on the clk that ads# is active. 18. bf, bf1, and cputyp should be strapped to v cc or v ss . 19. these signals are measured on the rising edge of adjacent clks at 1.5v. to ensure a 1:1 relationship between the amplitude of the input jitter and the internal and external clocks, the jitter frequency specturm should not have any power spectrum peaking between 500khz and 1/3 of the clk operating frequency. the amount of jitter present must be accounted for as a component of clk skew between devices. 20. brdyc# and buschk# are used as reset configuration signals to select buffer size. 21. the value of this signal may have been changed, check the latest pentium processor data book for the updated values. ** each valid delay is specified for a 0 pf load. the system designer should use i/o buffer modeling to account for signal flight time delays.
pentium ? overdrive ? processor with mmx ? technology e 46 9/8/97 11:55 am 29060701.doc intel confidential (until publication date) preliminary 5.6.4. timing and waveforms 290607-7 figure 7. clock waveform 290607-8 figure 8. valid delay timing
e pentium ? overdrive ? processor with mmx ? technology 47 9/8/97 11:55 am 29060701.doc intel confidential (until publication date) preliminary 290607-9 figure 9. float delay timing 290607-10 figure 10. setup and hold timing
pentium ? overdrive ? processor with mmx ? technology e 48 9/8/97 11:55 am 29060701.doc intel confidential (until publication date) preliminary 290607-11 figure 11. reset and configuration timing
e pentium ? overdrive ? processor with mmx ? technology 49 9/8/97 11:55 am 29060701.doc intel confidential (until publication date) preliminary 290607-12 figure 12. test timing
pentium ? overdrive ? processor with mmx ? technology e 50 9/8/97 11:55 am 29060701.doc intel confidential (until publication date) preliminary 290607-13 figure 13. reset and configuration timing 6.0. mechanical specifications 6.1. package dimensions the pentium overdrive processor with mmx technology, an upgrade for the 75, 90, 100-mhz pentium processor-based systems, uses a 320-pin ceramic staggered pin grid array (spga) package. the pins will be arranged in a 37 x 37 matrix and the package dimensions will be 1.95 2 x 1.95 2 (4.95cm x 4.95cm). see table 18. table 18. pentium ? overdrive ? processor with mmx? technology package summary package type total pins pin array package size pentium ? overdrive ? processor with mmx? technology spga 320 37 x 37 1.95 x 1.95 4.95cm x 4.95cm note: the mechanical specifications are provided in table 19. figure 14 shows the package dimensions for the pentium ? overdrive ? processor with mmx? technology.
e pentium ? overdrive ? processor with mmx ? technology 51 9/8/97 11:55 am 29060701.doc intel confidential (until publication date) preliminary table 19. package dimensions family: ceramic staggered pin grid array package symbol millimeters inches min max notes min max notes a* 33.88 solid lid 1.334 solid lid a1 0.33 0.43 solid lid 0.013 0.017 solid lid a2 2.62 2.97 0.103 0.117 a4 20.32 0.800 a5 10.16 air space 0.400 air space b 0.43 0.51 0.017 0.020 d 49.28 49.91 1.940 1.965 d1 45.47 45.97 1.790 1.810 e1 2.41 2.67 0.095 0.105 e2 1.14 1.40 0.045 0.055 l 3.05 3.30 0.120 0.130 n 320 spga pins 320 spga pins s1 1.52 2.54 0.060 0.100 notes: * assumes the minimum air space above the fan/heatsink. a 0.2 2 clearance around three of four sides of the package is also required to allow free airflow through the fan/heatsink.
pentium ? overdrive ? processor with mmx ? technology e 52 9/8/97 11:55 am 29060701.doc intel confidential (until publication date) preliminary aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa aaa 01.65 ref. s1 d l seating plane ref. 2 . 2 9 1.52 45 chamfer (index corner) pin c3 e2 d d1 a1 a2 a4 a a5 heat sink fan air space b e1 pp0077 aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aa a aa a aa a aa a aa a aa a aa a aa a aa a aa a aa a aa a aa a aa a aa a aa a aa a aa a aa a aa a aa a aa a aa a aa a aa a aa a aa a aa a aa a aa a aa a aa a aa a aa a aa a aa a aa a aa a aa a aa a aa a aa a aa a aaa aa a a a a a a a a a a a a a a a a a a aa aa aa aa aa aa aa aa aa aa aaaa aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaaa aaaa aaaa a a aaaa aaaa a a aaaa a aaa a aaa a aaa aaaa a a a a a a a a aaa aaa aaa aaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a 290607-14 figure 14. pentium? overdrive? processor with mmx? technology package dimensions 6.2. spatial requirements the pentium overdrive processor with mmx technology employs a fan/heatsink thermal management device. clearance requirements must be met around the fan/heatsink to ensure unimpeded air flow for proper cooling. figure 15 shows the pentium overdrive processor with mmx technologys fan/heatsink space requirements. the pentium overdrive processor with mmx technology has spatial requirements defined in the respective socket specification that must be met. as shown in figure 16, it is acceptable to allow any device (i.e., add-in cards, surface mount device, chassis, etc.) to enter within the free space distance of 0.2 from the pentium overdrive processor with mmx technology package if it is not taller than the level of the heatsink base. in other words, if a component is taller than height b, it cannot be closer to the pentium overdrive processor with mmx technology package than distance a. this applies to three of the four sides of the pentium overdrive processor with mmx technology package, although the back and handle sides of a zif socket will generally automatically meet this specification since they have widths larger than distance a. compliance to this requirement will ensure systems can be upgraded to the pentium overdrive processor with mmx technology.
e pentium ? overdrive ? processor with mmx ? technology 53 9/8/97 11:55 am 29060701.doc intel confidential (until publication date) preliminary 290607-15 note: z = 1.4 for pentium ? overdrive ? processor with mmx? technology . figure 15. illustrates physical space requirements for the pentium ? overdrive ? processor with mmx? technology temp figure 16. required free space from sides of spga package 6.3. socket 6.3.1. socket compatibility socket 5 (320 pins) and socket 7 (321 pins) are defined specifically for the requirements of the pentium overdrive processor with mmx technology. socket 5 and socket 7 define a fifth row of pins in the inside of the 296-pin spga socket. the rows e and aj are the new rows of pins defined by socket 5 and socket 7. socket 5 and socket 7 are a superset of the original 75, 90, and 100-mhz pentium processor (296 pins) pinout. the pentium overdrive processor with mmx technology sockets are compatible with their respective original pentium processors. to insure proper operation of pentium overdrive processor with mmx technology, all power and ground pins should be connected as defined by the re spective socket definitions. 6.3.2. socket 5 pinout socket 5 is the 320-pin zif (zero insertion force) socket recommended for the 150/166-pentium overdrive processor with mmx technology. the socket 5 pinout is defined with additional power and ground pins to ensure proper functionality of the pentium overdrive processor with mmx technology. the pinout is also specifically defined to ensure proper orientation for the pentium overdrive processor with mmx technology.
pentium ? overdrive ? processor with mmx ? technology e 54 9/8/97 11:55 am 29060701.doc intel confidential (until publication date) preliminary 12345678 9 12 34567891011 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 z y x w v u t s r q p n m l k j h g f e d c b a nc vcc5 vss vss an am al ak aj ah ag af ae ad ac ab aa z y x w v u t s r q p n m l k j h g f e d c b a vcc5 an am al ak aj ah ag af ae ad ac ab aa 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 vss vss vss vcc3 nc vcc3 vss vss nc vss vss vss vss vcc3 nc vcc3 vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss d20 d16 d13 d11 vss vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 d41 inc dp4 d45 d47 d38 d42 d36 d34 d32 d27 d29 d31 d25 dp2 d24 d50 d40 d44 d48 d39 d37 d35 d33 d28 d30 dp3 d26 d23 d19 d54 d46 d49 d52 dp6 dp5 d51 d53 d55 d58 d57 d60 d61 vss d43 d56 dp7 d63 d59 d62 d21 d17 d14 d10 dp1 d12 d8 dp0 vcc3 vss d22 d18 d15 nc d9 d6 d7 d4 d5 d1 d3 d2 picd0 picd1 vcc3 tdi tdo cputyp trst# nc nc vss vcc3 nc nc frcmc# bf vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss breq inc vss vss vss vss vss vss vss vss vss vss ap adsc# ferr# pm0bp0 bp3 bp2 inv cache# mi/o# pm1bp1 ierr# ken# ewbe# na# brdyc# wb/wt# phit# boff# brdy# ahold apchk# pbreq# pcd smiact# hit# lock# pchk# pbgnt# ads# hlda hitm# pwt inc eads# d/c# ignne# init rs# nmi d/p# a23 intr smi# pen# a24 a27 a25 a31 a3 a7 a29 a26 a21 prdy phitm# hold flush# vss w/r# vss vss vss vss vss vcc3 vss vcc3 vss vcc3 vss vcc3 vss vcc3 vss a10 vss a8 a4 a30 a6 nc a28 a22 picclk d0 tck tms# nc vcc3 stpclk# bf1 buschk# a20m# be0# be1# be2# be3# be4# be5# be6# be7# scyc clk nc reset a20 a19 a18 a17 a16 a15 a14 a13 a12 a9 a11 a5 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 290607-17 figure 17. 320-pin socket 5 6.3.3. socket 7 pinout socket 7 is a 321-pin zif (zero insertion force) socket recommended for future pentium and pentium overdrive processors and should be used for all new designs. socket 7 is pin compatible with the 320-pin socket 5 with the addition of a key pin. contact intel for further information.
e pentium ? overdrive ? processor with mmx ? technology 55 9/8/97 11:55 am 29060701.doc intel confidential (until publication date) preliminary 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 21 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 z y x w v u t s r q p n m l k j h g f e d c b a nc vcc5 vcc2 v ss v cc2 vss an am a l ak a j ah ag af ae ad ac ab aa z y x w v u t s r q p n m l k j h g f e d c b a vcc5 a n a m a l a k a j a h a g a f a e a d a c a b a a 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 21 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 v ss vss vss vcc3 nc vcc3 vss vss n c v ss v cc2 v ss v ss v ss v cc3 n c v cc3 v ss vss v ss v ss vss vss vss vss vss vss vss vss vss vss vss d20 d16 d13 d 11 vss vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 d41 inc dp4 d45 d47 d38 d42 d36 d34 d32 d27 d29 d31 d25 dp2 d24 d50 d40 d44 d48 d39 d37 d35 d33 d28 d30 dp3 d26 d23 d19 d54 d46 d49 d52 dp6 dp5 d51 vcc2 d53 d55 vcc2 d58 d57 vcc2 d60 d61 vss d43 d56 dp7 d63 d59 d62 d21 d17 d14 d10 dp1 d12 d8 dp0 vcc3 vss d22 d18 d15 nc d9 d6 d7 d4 d5 d1 d3 d2 picd0 picd1 vcc3 td i tdo cputyp trst# nc nc vss vcc3 nc nc frcmc# inc vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 bre q inc vss vss vss vss vss vss vss vss vss vss ap ads c# ferr# pm0bp0 bp3 bp2 inv cache# mi/o# pm1bp1 ierr # ken # ewbe# na# brd yc# wb/wt# phit# boff# brd y# aho ld apc hk# pbreq# pcd smiact# hit# lock# pchk# pbgnt# ads # hlda hitm# pwt inc eads# d/c# ignn e# init rs# nmi d/p# a23 intr smi# pen# a24 a27 a25 a31 a3 a7 a29 a26 a21 prdy phitm# hold flush# vcc2 vss w/r# vcc2 vss vcc2 vss vcc2 vss vcc2 vss vcc2 vss vcc3 vss vcc3 vss vcc3 vss vcc3 vss vcc3 vss a10 vss a8 a4 a30 a6 nc a28 a22 picclk d0 tck tms# nc vcc3 stpclk# inc buschk# a20m# be0# be1# be2# be3# be4# be5# be6# be7# scyc clk nc reset a20 a19 a18 a17 a16 a15 a14 a13 a12 a9 a11 a5 290607-18 note: shaded pins are internal no connects on the pentium ? overdrive ? processor with mmx? technology. figure 18. pentium ? overdrive ? processor with mmx? technology pinouttop side view
pentium ? overdrive ? processor with mmx ? technology e 56 9/8/97 11:55 am 29060701.doc intel confidential (until publication date) preliminary 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 z y x w v u t s r q p n m l k j h g f e d c b a nc vcc5 vcc2 v ss v c c2 vss a n a m a l a k a j a h a g a f a e a d a c a b a a z y x w v u t s r q p n m l k j h g f e d c b a vcc5 a n a m a l a k a j a h a g a f a e a d a c a b a a 10 11 12 1 3 1 4 1 5 16 17 1 8 1 9 20 2 1 22 23 24 25 26 27 28 29 30 3 1 32 33 34 35 36 37 v ss vss vss vcc3 nc vcc3 vss vss n c vss v c c2 v ss v ss v ss v c c3 n c v c c3 v ss vss v ss v ss vss vss vss vss vss vss vss vss vss vss vss d20 d16 d13 d 1 1 vss vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 d41 inc dp4 d45 d47 d38 d42 d36 d34 d32 d27 d29 d31 d25 dp2 d24 d50 d40 d44 d48 d39 d37 d35 d33 d28 d30 dp3 d26 d23 d19 d54 d46 d49 d52 dp6 dp5 d5 1 vcc2 d53 d55 vcc2 d58 d57 vcc2 d60 d61 vss d43 d56 dp7 d63 d59 d62 d21 d1 7 d14 d10 dp 1 d12 d8 dp0 vcc3 vss d22 d18 d1 5 nc d9 d6 d7 d4 d5 d 1 d3 d2 picd0 picd1 vcc3 td i tdo cputyp trst# nc nc vss vcc3 nc nc frcmc# inc vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vcc3 vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 br eq inc vss vss vss vss vss vss vss vss vss vss ap adsc# ferr# pm0bp0 bp3 bp2 inv cache# mi/o# pm1bp1 ierr# ken# ewbe# na# brdyc# wb/wt# phit# boff# brdy# ahold apchk# pbreq# pcd smiact# hit# lock# pchk# pbgnt# ads# hlda hitm# pwt inc eads# d/c# ignne# init rs# nm i d/p# a23 intr smi# pen# a24 a27 a25 a31 a3 a7 a29 a26 a21 prdy phitm# hold flush# vcc2 vss w/r# vcc2 vss vcc2 vss vcc2 vss vcc2 vss vcc2 vss vcc3 vss vcc3 vss vcc3 vss vcc3 vss vcc3 vss a10 vss a8 a4 a30 a6 nc a28 a22 picclk d0 tck tms# nc vcc3 stpclk# inc bu schk# a20m# be0# be1# be2# be3# be4# be5# be6# be7# scyc clk nc reset a20 a19 a18 a1 7 a16 a15 a14 a13 a12 a9 a1 1 a5 290607-19 figure 19. pentium ? overdrive ? processor with mmx? technology pinoutpin side view
e pentium ? overdrive ? processor with mmx ? technology 57 9/8/97 11:55 am 29060701.doc intel confidential (until publication date) preliminary 7.0. thermal specifications the pentium overdrive processor with mmx technology is shipped with an attached fan/heatsink for a complete thermal solution for the processor upgrade. the fan/heatsink cooling solution will properly cool the pentium overdrive processor with mmx technology provided the space requirements of section 6.2 are met and the maximum air temperature entering the fan/heatsink (t a ) does not exceed 45c. the fan/heatsink inlet temperature (t a ) is measured 0.3 above the centerline of the fan hub at the system maximum ambient operating temperature (see figure 15). 8.0. testability 8.1. introduction this section describes the features which are included in the pentium overdrive processor with mmx technology for purposes of testability of the part. the testability features provided for the original pentium processor are also available on the pentium overdrive processor with mmx technology. the pentium overdrive processor with mmx technology however, does not support the ieee standard 1149.1 boundary scan using the test access port (tap) and tap controller as described in chapters 11 and 27 of the pentium ? family users manual, volume 1 . contact your intel representative for further details. some features of testability are described below. 8.2. built in self test (bist) self test is initiated by driving the init pin high when reset transitions from high to low. no bus cycles are run by the pentium overdrive processor with mmx technology during self test. the duration of self test is approximately 2 19 clocks. bist is used to test approximately 70% of the devices in the pentium overdrive processor with mmx technology. the pentium overdrive processor with mmx technology bist consists of two parts: hardware self test and microcode self test. during the hardware portion of bist, the microcode and the large plas are tested. all possible input combinations of the microcode rom and plas are tested. the microcode self test is done by comparing the stored value of rom check sums with the result of the self test. if a mismatch occurs or errors are detected during bist, the pentium overdrive processor with mmx technology will assert the ierr# pin and attempt to shutdown. 8.3. tri-state test mode when the flush# pin is sampled low in the clock prior to the reset pin going from high to low, the pentium overdrive processor with mmx technology enters tristate test mode. the pentium overdrive processor with mmx technology floats all of its output pins and bi-directional pins including pins which are never floated during normal operation (except td0). tristate test mode can be initiated in order to facilitate testing of board connections. the pentium overdrive processor with mmx technology remains in tristate test mode until the reset pin is toggled again.

e pentium ? overdrive ? processor with mmx ? technology 59 9/8/97 11:55 am 29060701.doc intel confidential (until publication date) preliminary appendix a pentium ? overdrive ? processor with mmx? technology upgradability design considerations intel has designed the family of pentium overdrive processors so that they can be easily installed by the end- user. pc manufactures can support this by implementing the design considerations listed in table 20. table 20. design considerations design consideration implementation visible pentium ? overdrive ? processor with mmx? technology socket the pentium overdrive processor socket should be easily visible when the pcs cover is removed. label the pentium overdrive processor socket and the location of pin 1 by silk screening this information on the pc board. accessible pentium overdrive processor socket make the pentium processor easily accessible to the end user (i.e., do not place the intel pentium overdrive processor socket under the hard disk). if the low insertion force (lif) is used, position the pentium overdrive processor socket on the pc board such that there is ample clearance around the socket. foolproof chip orientation intel packages all pentium overdrive processors with a keyed pin configuration that insures that the pentium overdrive processors fits into the respective sockets in the correct orientation. zero insertion force upgrade socket the high pin count of the pentium overdrive processors often require more than 60 lbs of insertion force for low insertion force (lif) sockets. a zero insertion force (zif) socket insures that the chip insertion force does not damage the pc board. if the zif socket has a handle, be sure to allow enough clearance for the socket handle. if a lif socket is used, additional pc board support is recommended. plug and play jumper or switch changes should not be needed to electrically configure the system for the pentium overdrive processor. thorough documentation describe the pentium overdrive processors installation procedure in the pcs users manual.
pentium ? overdrive ? processor with mmx ? technology e 60 9/8/97 11:55 am 29060701.doc intel confidential (until publication date) preliminary appendix b pentium ? overdrive ? processor with mmx? technology zif socket vendors the following list provides examples of sockets which can be used for pentium processor-based systems. note this is not a comprehensive list, intel has not tested all of the vendors sockets listed below and cannot guarantee that these will meet every pc manufacturers specific requirement. socket no. style drawing no. part no. amp socket 5 slaz, oc, t c-916513 916513 (800) 522-6752 socket 5 slaz, oc, t c-916560 916560 socket 5 slaz, oc, t c-916655 916655 socket 5 slaz, oc, t c-916656 916656 socket 5 slaz, oc, t c-916671 916671 socket 5 slaz, oc, t c-916672 916672 socket 7 slaz, oc, t c-916637 916637 socket 7 slaz, oc, t c-916657 916657 socket 7 slaz, oc, t c-916658 916658 appros socket 5 slaz, oc, t kea391129 slr-s19-320-ln2 (408) 567-1234 socket 7 slaz, oc, t kea391130 slr-s19-321-ln2 average plating thickness used for qualification testing: 11.2 micro inches gold. augat socket 5 slaz, oc, t mp-ax159bcd20 mp-ax159bcd203 (800) 999-7646 socket 5 slaz, oc, t mp-ax159bcd20a mp-ax159bcd203a socket 5 slaz, oc, t mp-ax159bcd20b mp-ax159bcd203b socket 7 slaz, oc, t mp-ax164bcd21x mp-ax164bcd213 socket 7 slaz, oc, t mp-ax164bcd21xa mp-ax164bcd213a socket 7 slaz, oc, t mp-ax164bcd21xb mp-ax164bcd213b average plating thickness used for qualification testing sockets: 19 micro inches gold.
e pentium ? overdrive ? processor with mmx ? technology 61 9/8/97 11:55 am 29060701.doc intel confidential (until publication date) preliminary socket no. style drawing no. part no. berg/mckenzie socket 5 slaz, oc, t sal b 270086-000 zif 97050-4020 (510) 654-2700 socket 5 slaz, oc, t sal b 270086-000 zif 97050-4120 socket 7 slaz, oc, t sal b 270088-000 zif 97054-4020 socket 7 slaz, oc, t sal b 270088-000 zif 97054-4120 average plating thickness used for qualification testing sockets: 35 micro inches gold foxconn socket 5 slaz, oc, nt 309-0000-049 pz32023-0120 (408) 749-1228 socket 5 slaz, oc, t 309-0000-049 pz32033-0120 socket 5 slaz, oc, t 309-0000-049 pz32043-0120 socket 5 slaz, oc, t 309-0000-049 pz32053-0120 socket 7 slaz, oc, t 309-0000-062 pz32143-0120 socket 7 slaz, oc, t 309-0000-062 pz32153-0120 average plating thickness used for qualification testing: 10.0 micro inches gold jae socket 5 slaz, oc, t sj029842-e pcps-zl320-a9 (714) 753-2628 socket 7 slaz, oc, t sj029842-e pcps-zl321-a9 average plating thickness used for qualification testing: socket 5/7 3.7 micro inched gold flash/31.4 microinches palladium nickel, socket 8 4.5 micro inched gold flash/34 micro inches palladium nickel. producer socket 5 slaz, oc, t pd104-3202 pd104-32025 886-2-202-3578 average plating thickness used for qualification testing: 5.7 micro inches gold. yamaichi socket 5 slaz, oc, t kl-13790 np210-320-0100-cc0 (800) 769-0797 socket 5 slaz, oc, t kl-13425 np210-320-0100-cc1 socket 5 slaz, oc, t kl-13518 np210-320-0100-cc2 socket 5 slaz, oc, t kl-13930 np210-320-0100-cc3 socket 5 slaz, oc, t kl-13625 np210-320k13625(d) socket 7 slaz, oc, t kl-13823 np210-321-0100-cc1 socket 7 slaz, oc, t kl-13620 np210-321-0100-cc2 socket 7 slaz, oc, t kl-13938 np210-321-0100-cc3 average plating thickness used for qualification testing: 6.1 micro inches gold.

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